EDA and the 50 picosecond problem, part 2

There has been a lot of introspection and analysis recently, by EDA executives and analysts as to why we are where we are, as an industry.    There seem to be no easy answers as to why EDA is at the bottom of the economic food chain, in-spite of the stellar growth and demand for electronic devices. We can blame the recent economic crisis, declining ASIC design starts, rising mask costs etc. but the writing was on the wall much before the market meltdown.

There maybe a variety of reasons as to why there maybe a lack of significant differentiation amongst physical design tools, as discussed in the previous segment, some of which are highlighted below.

Cost of EDA software development is extremely high compared to any other segment of the software industry. For a startup to shine and differentiate itself, it has to build the mundane first (foundation, database, file format support), before attempting to show it’s value proposition. By the time the foundation software layer is done, there are significant cost pressures for the startup to scale-back it’s differentiation and compete head on with incumbent products on features.

The cost of sales in EDA is high, not in the traditional accounting sense, but when we look at a typical sales cycle. An EDA tool ‘benchmark’ can last for months, extending the sales cycle to a degree where it ceases to make financial sense for a startup company.

The large EDA vendors do innovate significantly but tend to be encumbered by their existing customer base, and choose to focus on incremental rather than disruptive innovation.

So what is the answer for us an industry to get out of this slump ?

Reduce the cost of EDA software development.This will require EDA companies to devote significant effort on an ‘open-source’ like paradigm.

Engage with universities to encourage the next generation of EDA developers with fresh ideas. This may lead to us finding the 100 picosecond or 1 nanosecond differentiator.

Short circuit the long benchmark cycles by enabling web deployable tools and focus on ease of use.This is perhaps easier said than done, due to the complexity of EDA software tools, but it is a necessary step for the industry to jettison out of an archaic business model.The burden lies on the creativity of EDA developers to make tools easier to use and deploy.

Large EDA companies need to step up and encourage disruptive innovation, either through funding or feeding the software ecosystem. Companies like Cisco Systems have mastered the art of spin-offs and spin-ins,. While on the other hand, companies like Google and Yahoo have contributedsignificantly to the ‘open source’ software ecosystem. EDA industry should follow these model to accelerate innovation.

There are significant technical challenges for EDA developers to solve and capitalize on. Some technical challenges that come to mind are the following: Power distribution, Fine-grain on-chip voltage control, semi-synchronous logic, system level compilers for hardware-software partitioning.

Merging EDA with circuit IP can expand the market segment, while adding significant additional value to our customer base.This notion has been tried in past with marginal success. Perhaps the timing is right for these activities to accelerate and morph into a new business model for EDA.

Next generation of EDA entrepreneurs need to build companies without an overwhelming focus on an ‘exit strategy’, and not being shy about building profitable ‘lifestyle’ companies. Some of the most successful companies in the electronics industry were built on the premise of adding value to the engineering community, and not with a focus on how to ‘exit’.

Some of the answers to our industry’s problems lie in our ability to efficiently innovate out of the economic slump and to pay attention to creating differentiated products.

There has been a lot of introspection and analysis recently, by EDA executives and analysts as to why we are where we are, as an industry.    There seem to be no easy answers as to why EDA is at the bottom of the economic food chain, in-spite of the stellar growth and demand for electronic devices. We can blame the recent economic crisis, declining ASIC design starts, rising mask costs etc. but the writing was on the wall much before the market meltdown.

EDA ecosystem revisited

One can point to many issues with the EDA industry, and attempt to root cause why we are not being able to get a bigger piece of the semiconductor pie. Few things that come to mind are the following:

The venture capital community seems to look at EDA as a broken business model, with little or no upside, due to the lack of recent exits. An investor recently told me and I quote “The smallest ROI per Phd. is in the EDA industry”.

Large EDA vendors are not feeding the ecosystem.There has been little or no funding for startups or academic research from the large EDA vendors. In addition there is less and less collaboration from the large EDA vendors.While this approach is conceivably good to protect ones’ franchise, it maybe a flawed strategy for the long term, in a technology driven industry such as ours.

Funding for research institutions has fallen out of favor with EDA companies.This is a disturbing trend, considering the fact that a majority of the foundation of EDA software comes from university research.

Large EDA vendors want to mimic the enterprise software (Oracle, SAP) monolithic model. This sounds very attractive to a CEO of an enterprise, as compared to a heterogeneous ‘best-in- class’ model, which would entail internal support and development.The one difference in EDA versus enterprise software, is perhaps the fact that FASB (Financial Accounting Standards Board) or GAAP (Generally Accepted Accounting Principles) rules don’t change at the rate at which the semiconductor process or design requirements change.

EDA startups have always relied on Angel investors who were as passionate about EDA technology as the founders.This is another very important source of capital that is drying up, and is perhaps the one that has serious implications for us as a technology industry. If successful EDA “Angels” don’t feel comfortable investing in our industry, this say’s that we have a serious problem on our hands.

Semiconductor industry (our customer base) has been slow to adopt new technologies, due to cost pressures. In addition they have got used to getting products for a fraction of what they used to spend 5 years ago.This trend compounded by a lack of pricing discipline from the EDA vendors has lead to significant price and value erosion.EDA industry’s disaggregated software ecosystem is clearly hurting the industry. If companies differentiate themselves based on a file format ( CPF versus UPF for instance) , we have some critical thinking to do, as an industry. Efforts such as Open-Access have not gained the traction they should have to propel our industry from competing on issues that add little or no value, such as proprietary file formats. Perhaps ‘Open-Access’ needs to be more ‘open’.

The 50 picosecond problem

The final problem that comes to mind is what can be termed as the ‘50-picosecond problem’. This is a problem where innovation seems to stall when an industry segment nears maturity.

In order to highlight the ’50 picosecond problem’ we can try to analyze the IC physical design tool segment of the EDA industry, as an example.

IC physical design tools from Company S, Company C , Company M and Company M can take the same design and produce results within 50 picoseconds (figure of speech rather than a literal) of each other.

What this highlights is a lack of differentiation amongst physical design tools. In addition, we see new startups in the physical design space, that develop a tool from ground up, only to be marginally better (50 picoseconds ?) than the incumbent tools.

What could be reason for such incremental differentiation in products that are developed from ground up, with the premise of displacing incumbent tools ? Perhaps all the engineers are reading the same books, and implementing the same algorithms again and again ? Could it be that the semiconductor process is scaling so well, that there are no new disruptive physical effects ?

No easy answers

We will attempt to address some of the issues highlighted above in a later blog entry.

How I got to Japan

The PA system at work announced that I had a call. It was from Dr. Steve Butner, my graduate advisor at UC Santa Barbara. He was very excited. “John, I just got some information about this program that was just made for you.” He explained that the American Electronics Association was sending electrical engineering and computer science graduate students to an intensive Japanese language course, and then on to work as an engineer in Japan. The goal of the program was to balance the exchange of engineering students between Japan and the US.

I had already taken two years of Japanese classes. I dreamed of applying the language at work in Japan, but I had no way to actually make this happen. The American Electronics Association Japan Research Fellowship was the opportunity of a lifetime to realize my goal. I applied, and was accepted. Had the program never found me, my dream would have just quietly faded away.

The fellowship was a full ride: airfare, room and board, tuition at Cornell, and a job as a chip designer at Intel Japan. All of this was a tremendous gift for which I am eternally grateful. Only the power of a major industry association could make something like this happen.

I too was going to pay. This episode of my life was like a card game in which I held a great hand, but nonetheless discarded graduate school, my girlfriend, job, friends and Santa Barbara, retaining only my electronic engineering card. Then I was dealt new cards I could not even recognize. How would I assemble them into a winning hand?

The program started with the Cornell University FALCON Japanese language summer session. This was superb. I was very serious and studied hard. When I started, I had an understanding of Japanese grammar, writing and vocabulary, but I could not really hold a conversation. Just nine weeks later, I could carry on relationships with people entirely in Japanese. I have never learned so much so quickly.

I vividly remember seeing Japan for the first time from the air. All this preparation, and I had never even been there. I hired a taxi and chatted with the driver in Japanese along the way to my destination. Using a new language in country for the first time is the most exhilarating of experiences.

I arrived in Tsukuba, where a tiny apartment awaited me. It had a murphy bed, a basic kitchen, a bathroom and a television, which was to be my language teacher and only friend for quite a while. My private apartment was a palace compared to the barracks provided to the other AEA Japan Research Fellowship participants. Intel even gave me a new Toyota Corona to drive.

My job at Intel Japan was verification and circuit simulation for the 8253 counter/timer portion of a microprocessor. As you might expect, many signals described a count. Engineers and programmers usually abbreviate this common word as “cnt”, but the Japanese designer chose to delete only the “o” in “count”. It made for the most profane RTL and netlist I have ever seen.

Intel Japan is based in Tsukuba, a “Silicon Valley” created artificially by the government. These are the same people who brought you Narita Airport, located an hour away from the city it serves. Tsukuba is in Ibaragi-ken, which is famous for backwardness. The nearest train station was 30 minutes away by car. In Japan, a city without a train station is nowhere. I hated living there, and so did many others. All the foreigners at Intel Japan were plotting their escape to Tokyo. Some Tsukuba residents escaped in a more tragic way. The suicide rate was so high that Tsukuba had its own trademark method of suicide–Tsukuba diving, throwing oneself off Tsukuba Tower.

Instead, I threw myself into improving my language skills, the goal for which I had sacrificed so much. This meant using exclusively Japanese. It also meant extreme isolation, as I was not a particularly engaging conversationalist. Still, I was good enough to carry out my duties at Intel in Japanese, speaking English only to my boss (a wise compromise). In an EE Times interview I declared, “I’m known as hardcore about not speaking English in the office. I am definitely looking at getting very good at Japanese.” Ah, such youthful bravado. Hardcore indeed.

My colleagues at Intel were more sophisticated than the locals, and they were kind to me. In the winter, we went skiing almost every weekend. I made some good friends at Intel Japan. After about six months, the loneliness and culture shock started to subside.

Originally my internship was six months, but I was just starting to get the hang of things, so I extended to one year. Intel Japan was good to me, but they only had engineering work in Tsukuba. As the end of my year came to a close, I conducted a job search, and landed a position in Tokyo. After a few years, I returned to finish graduate school at UCSB, then set out for Japan again. The AEA Japan Research Fellowship had succeeded in its goal of turning me into an engineer who could navigate Japan.

 JohnB is in the house…Will EDA ever be the same?

Day 10 in my new CMO gig at Cadence…

After 100s of meetings, I have 1000s of thoughts relating to my new favorite obsession — EDA. Market dynamics, ecosystem, competitive landscape, conventional wisdom, business models, growth segments, product direction, pricing and packaging — the list of challenges goes on and on. 

But the one observation – beyond all the others – that completely blows my mind is the intense cynicism from friends surrounding my decision to join Cadence. On pretty much a daily basis, I‘m asked, “Why John, would a marketing guy like you make a move to EDA?” Translation: “What the hell were you thinking?”

I’m just two weeks in and unquestionably confident that my decision was right. How can I be so sure? Well, I can clearly pinpoint the exact thought process behind the decision and it all started when I read one simple article.

I’ve learned from experience that it’s easy to know when it’s time to leave a job, but it’s really hard to know where to go. Thankfully, my fellow critical thinkers, this industry has many pundits who have outlined “the rules” that are meant to help us find the light as we make our way up the path of advancement. “The rules” give us generally accepted principles or tribal wisdom by which most people should judge a new opportunity.

As luck would have it, I happened across an article published on Fortune.com that was skillfully written by a seer of great industry insight and highlighted the 10 things to look for in a “LEGENDARY” job. I recognized them right away – this article covered “the rules” in all of their well-acknowledged, well-heeded glory. 

Things to look for in a “legendary” job like…

Number 1: a company in a growing market with a strong brand and leading position.

And number 2: a company with products that customers view as aspirin (read: essential), not vitamins (a supplement). In bad economies no one takes their vitamins

And number 3: a strong balance sheet with lots of cash

And number 4: a legendary executive team.

And numbers 5, 6, 7, 8-10. All more of the same!

Ten things no one would argue with, right? Pretty obvious stuff for a successful enterprise. I read each recommendation closely and then to be sure, I read them again. Only I came to a different conclusion. Companies that already have these ten things going for them don’t need much marketing help.

I mean, who needs great marketing if the company already is the market leader, in a growing market, with the leading brand and the leading market position, with products that are absolutely essential, all supported with an awesome balance sheet?

Maybe I look at the world a bit differently than most people, but I aspire to be a great marketer and to meet a great challenge. To actually accomplish something extraordinary, I knew I was going to have to break “the rules”.

So why EDA? Here it is – short answer. EDA is an industry that needs to reacquaint itself with “legendary” marketing.

Let me tell you why I think so. EDA is a critically important industry. It matters, but somewhere along the way it has forgotten that it matters. The super complex, increasingly powerful, application-rich chips that are required in every device that is produced today CANNOT be developed without EDA tools.

However, this industry is in desperate need of leadership and vision. There’s a transformational business and technology shift changing the way that companies develop silicon. We’re at one of those inflexion points that comes once a generation. I strongly believe the company that enables and accelerates this transition will become the undisputed leader on all fronts: innovation, technology, thought and market.

EDA used to be exclusively about design. I’ll even pay homage to Intel’s symbolic team of engineering rock stars portrayed in its recent ad campaign. In the past, Intel-esque rock stars designed the chips we know and love. It was their goal to constantly make chips smaller, faster, with higher quality and reliability. Basically, these rock stars have continuously innovated all of the IP on a chip – every last piece of it. It isn’t like a friendly game of Guitar Hero either. The rock stars in this game have to spend a massive amount of time acquiring the resources and skills necessary to even start thinking about playing. You can’t fake it – there’s no air guitar.

Nowadays, it’s a fact — every industry is up against ever-increasing time, cost, quality and global competition constraints. I see some forces aggressively beating our industry’s “rock star model” into submission: the physics challenging the continuation of Moore’s law, the increasing importance of software that is embedded and the applications that run on chips. It takes too long, costs too much and worse, the quality is never where it needs to be. There is a tremendous amount of risk involved. It is impossible for one company to afford to keep all of the rock stars under one roof.

These forces have led the chip design process to a point of discontinuity. Integration is becoming just as important as design — integration of analog and digital IP, tighter and earlier integration of every stage of the design process, integration of heterogeneous, multiple cores on a single chip, integration of hardware and software. These and other integration challenges will forever change the semiconductor companies and their value chains.

EDA must rise to meet its customers’ changing requirements. Our customers need help in the transition to a business model that can meet the cost structure, meet the time constraints, and deliver quality in a more complex world. The rock star model must evolve. Rock stars will still create amazing IP, but “system integrators” will be equally important in the value creation equation.

These system integrators will work with internal and external IP rock stars, and even their end systems customers, using distributed systems. Hardware and software teams will be managed using executable specifications and metrics that bring more predictability to schedules, just as the complex system integrators do in the embedded software world that I come from.

That’s right, I spent the last five years in embedded software going through a very similar industry transformation. I know from experience what a shift to an inte
gration model looks like. Similar to embedded software, a community of experts in the EDA industry is forming and actively gaining momentum. They can’t be stopped and they won’t be ignored. They’re driven by fundamental economic forces. This EDA community is quickly developing a system integration model that can be broadly used and reused by the entire industry. But what comes next?

The way I see it, no one has answered the call of the community. No one has stepped up, raised their hand and focused on making sure our customers have the tools and techniques they need to face the coming challenges of the industry.

Well look closely, because my hand is up!

A great company is going to seize this opportunity. At the end of the day, this company will have achieved legendary results and be able to boast all of “the ten things to look for” mentioned in the Fortune article. This company will be THE “legendary” EDA company. This vision is why I joined Cadence. 

Over the years, I have developed many “Belief Bricks”. What are these, you ask? These are the building bricks that define my foundation for explaining the world around me. We all have them – they are a filter by which we accept input and shape our ideas. I’d like to pick out one of them here and connect it to a trend in our industry – it’s the “Law of Unmet Needs”.

I like this one – it is the root of business opportunity. Do this: find what is painful and getting worse, and no one (seems to be) addressing it. Then figure out a (market-feasible) approach for how to solve it, use good business skills to manage the solution, add water – and voila!

Of course it’s not quite that simple. Yet it remains the basic recipe for “business plans” supporting new startups, or new products within existing companies. It is the basis for how we approach our new standardization efforts at Si2 as well. Part of the trick is truly understanding what the market is telling you about the unmet need, while part is navigating hazards that must be deftly avoided to not fall into the abyss along the way.

One benefit of my role at Si2 is the opportunity to listen to a wealth of input from across our member companies. Recently, there has been a noticeable increase in the pain level associated with designing complex silicon that runs embedded software. This trend was already there, as more processors run more software on SoCs. What has changed, however, is the added risk this embedded software “variable” brings to achieving necessary parameters of the hardware design task. 

One working group in Si2′s Low-Power Coalition, while addressing power at the architecture / ESL level (where 80% of the savings are hidden), concluded that a lack of standards for higher-level modeling of power was a barrier to industry progress. Now, even without an embedded software component, the challenges of estimating and managing power consumption during the product’s operation are hard enough. Yet many products today have multiple processors, and this trend will continue. Your smart phone’s silicon burns power dictated by the software that owns the bulk of digital functionality. The energy dissipation resulting from switching transistors is a direct consequence of the software operation… but EDA flows lack a means to factor that into the design trade-off space. What operations must be concurrent? What impact will switching power / frequency modes have to critical response times as timing fluctuates? Which architecture is best suited to the combined (software + hardware) time-varying functionality? How do we cooperatively work with the software team better?

This problem does not lend itself to simple in-house solutions. Its no wonder that we are hearing so much about the rising cost and complexity of designing silicon – to the point that the venture capital community has “moved on” to other (more attractive) areas. There clearly seems to be a large unmet need, and this trend has nowhere to go but up. 

In the past, established EDA vendors have stated they have rejected this growing aspect of design because there is no money in the “software world” (think free compilers and $995 development kits). However, that logic is flawed. To compete in the software development world is to address a different problem – and one that already has plethora of solutions. The unmet need here is addressing the current problem scoped by EDA: effective design of silicon to requirements under a number of complex constraints. EDA adapted to adjacent manufacturing issues and integrated DFM concerns; perhaps software is the next adjacency. How much would companies pay for genuine improvement in this problem, where the new world order puts embedded software onto nearly every chip? How can we design to even more stringent requirements 5 years from now if this trend continues?

Perhaps this problem area is not being addressed because we lack a clear vision of any feasible approach for connecting our world of silicon design and the world “on the other side”. Perhaps no single company can deliver a useful solution without more enabling infrastructure to support it. Perhaps we haven’t really tried yet.

I see a continuation of the trend for more embedded processors – and more complex silicon design parameters dependent upon what the software does that drives its operation. What do you see? Is this really an unmet need? If so, how would you propose the industry tackle it? I would be interested to hear your comments.

DAC 2009: a Wall Street perspective

Industry & technology trends: In the 2009 show, there were a set of new and not-so-new issues (comparing with DAC 2008) that are worth mentioning namely:

• Analog/mixed-signal, a.k.a. “custom IC”, a vital franchise for CDNS (usually a fourth or more of its revenues, and probably an even higher portion of its earnings, and where SNPS has made its at-long-last entry);
• Power (the tools and methodology for which have only grown in importance in recent years, although “power analysis & optimization” is relatively small as a discrete EDA reporting category). Power considerations will need to be taken into account throughout the design process (with implications therefore for how the main vendors enable and package their tools). As MENT noted in a product introduction breakfast on July 27th, “system-level optimization” has the biggest impact on power consumption”. Related to that, MENT’s main announcement at the show was of “Vista”, its “architecture-level” power platform.
• System-level design (representing higher level of abstraction, which is usually a rationale for new growth in EDA). This has now become a $200M+ reporting segment, in which MENT believes it has about a 40% share; and, somewhat more esoterically,
• 3D “stacking”, a new technique for designing and packaging ICs (a big deal for ST Micro for instance, as it publicly noted).

Industry revenues, product mix, and bookings:

• According to the latest EDA Consortium (EDAC), EDA license, maintenance, and services revenues were $1.051 billion in 1Q09, down 10%. Not surprisingly, the largest decline was in “license & maintenance”, down 13% to $850 million. The three largest vendors accounted for 70% of the total industry for the quarter, towards the low-end of the 70%-75% range. The difference was largely attributable to the revenue decline at CDNS.
• According to the EDAC data, the five largest product categories were (remain): IC implementation (11% of industry revenues); PCB (11%); Logic Verification (13%); Analysis tools (8%); Synthesis (6%); RET EDA (5%) and Analog/mixed-signal simulation (5%), or a total of 59%. Of these, the only one that grew in the most recent quarter was RET.
• For the trailing twelve-months ending 1Q09, the industry revenue was $4.484 billion, down 12%, vs. the trailing-twelve months ending 1Q08, including a 17% decline in license & maintenance revenues for the industry.
• Over that same period, the combined product bookings of the top three vendors declined ≈35% to about $2.05 billion, mostly because of the plummet at CDNS and the comparison with the large SNPS renewal at Intel in mid-2007. The 2Q data will come out once MENT, LAVA, and SNPS report their July 2009 quarterly results.
• I’m estimating combined revenues for the top 3 for 2009 of about $3.033 billion (down 5%); combined non-GAAP operating income of about $315 million (or 10% of combined revenues; combined cash flow of under $250 million; and combined bookings of about $2.01 billion, with a weighted average duration of over 3 years.
• Anecdotally, no customers with whom I met at DAC spoke of planning to increase run-rates, with the preference being apparently to keep even the best-performing suppliers “stable”. Indeed, the disparity between gross bookings and average durations might imply some lower run-rates in some cases when looking at aggregate bookings for the main suppliers.

 Other industry odds-and ends:

With the possible further consolidation of semiconductor companies, or parts thereof, the issue of the transferability of licenses (or the lack thereof specifically) may become an important issue for investors, since there may be instances of some new bookings or re-bookings in some circumstances, depending on scenarios like: Parent company licensee merges with another parent company licensee; Divisional licensee is spun off into a new joint venture entity.

In a keynote address by TSMC’s v.p. of design & technology platforms on “Overcoming the new design complexity barrier”, there were a number of interesting observations and recommendations for the industry (presumably premised too on what would be good for TSMC): the industry is at a “cross-roads” of complexity and affordability; there is a widening gap in terms of the growth of wafers produced and the number of tapeouts (due to growing complexity and cost per design), necessitating a need for more design/manufacturing collaboration, more reuse, and the need for avoidance of redundancies.

At a DAC “management day” panel with senior design executives from Intel, LSI, ST, Infineon, Global Unichip, TI, and Freescale, there was little or no gratuitous EDA-bashing but instead quite reasonable observations about how best to go about the business of designing chips in a timely and economical manner. There were some noteworthy comments and responses on questions having to do with: 1) What they want from their EDA vendors: optimize across different domains (Intel), analog (LSI), chip/package co-design (ST); 2) DFM: unlike design-rule checking DFM is not “black & white”, OPC is a “moving target (ST); very important, developing their own tools (TI). There was also some discussion about (the need for) “software management tools” for design. There is an important difference of scale here as the latter market has order of magnitude more users than are likely to be available in EDA, notwithstanding the extraordinary complexity of chip design. There might finally be a product opportunity here.

Cadence Design Systems. As a very general statement, CDNS’ technical position remains steady, though some customers concurred with the notion that the kind of relative steep improvement we saw from 2001-2006 (pursuant to CDNS’ successful acquisition integration strategy) has run its course. CDNS’ software bookings implosion last year (about -60%) and the further decline this year (down by a further mid-teens percent to under $400 million, which would be, quite unusually, less than MENT’s this year), don’t have much to do with technology (unlike the situation in 1999) so much as semi/industry cyclical reasons and of course the contracts renewal abyss. Given the depths of the recent bookings decline it seems unlikely that CDNS will get back to “normal”, i.e., 2005-2006, annual software bookings levels before 2011, if then.

Mentor Graphics. The main thing Mentor talked about at last year’s DAC was integrating the Calibre physical verification/DFM platform with its Olympus-SoC place & route system (acquired via Sierra Design in 2007). There has since been progress here, which is quite important (see too TSMC’s Reference Flow 10 announcement). For the year, MENT might be able to eke out a small year/year bookings gain, assuming they have a large enough sequential gain in 4Q. The same might be said of SNPS for the year.

Synopsys. In the critical area of IC implementation (one of the largest in all of EDA), SNPS is now seeing the returns from the past 6-7 year path of integrating Avant!’s technology with own, and maturing that combination, e.g., IC Compiler (a large portion of the “core” EDA reported revenues). On the other hand, not s
urprisingly, standalone synthesis has been a declining category for the industry. Granted there are important issues of contact timing, but it’s conceivable that even next year SNPS’ bookings could still be double those of CDNS (underscoring the importance of CDNS’ cost cuts and efforts to improve cash flow).

Expats, natives or nuts

I have lived in 6 countries so far, in most of them more than once.

If you move to a radically different environment you have three options: hang out with expats, go native or go nuts.

I have done all three of those. In my opinion people enjoy the company of other people like themselves. If you travel around the world you don’t really do it to connect to the people of Borneo, you want to chug beers with the other backpackers. Hence the three options: find people like you in a strange place, become like the natives or become really lonely.

This is particularly relevant for couples or families who move together. You can have the working businessman who lives in expat land, his lonely wife who goes nuts and their kids who go native.

I found learning the local language quite hard. It is an essential prerequisite for the going native option. If you hang out with expats, you can avoid learning the language altogether. I have met many people who have lived in a foreign country for decades and have avoided learning the merest basics of the local language. This applies equally to American businessmen in Paris, to Brits in Hong Kong and the wives of Turkish immigrants in Germany.

My advice would be to commit early and seriously to study the language, preferably starting before you actually move there (I have never managed to do this myself, but I have seen impressive results in some of my friends who have).

Even if you don’t go native, learning the language will enhance the experience multi-fold and allows you to create some connection to the locals. Signing up for lessons also a good way to meet other foreigners, who have much in common with you in finding this country new and strange.

Kids tend to go native if you send them to a local school. When they are at primary school age I have found that they have a strong urge to conform and belong to a group. Don’t be surprised if they reject their own nationality and mother tongue. I don’t think there is ever an age when you should rule out moving abroad with children, but clearly it is not for every kid – or adult.

Children are naturally conservative and will never want to leave their current friends and lifestyle for something new that they can’t even imagine. You would have to ignore your kid’s inevitable reservations but they rarely take the "going nuts" route. In all probability they will make friends with natives or expats and won’t want to leave again.

If the opportunity to move abroad does arise do think twice. One thing is for sure, it will shape your life.

Value Proposition

When purchasing decisions for complex, high-tech products are made based mainly on price, users get the short end of the stick. They often end up having to get the job done with tools that are less capable than others on the market. This means they have to work harder to hit schedules, or that schedules slip and their company doesn’t make as much money as it could. Decisions based on value instead of price often yield better results for those organizations prepared to make them.

Buying based on value doesn’t always mean paying a high price, but it does mean  looking beyond the idea that tools are an expense, and finding ways to reduce the overall effort of designing and verifying chips. While price-based decisions are relatively easy, decisions based on value are more complex. Determining the value of a product requires looking beyond its price, and really understanding the return on investment (ROI) the organization can get by acquiring the product. Will the tool save time? Will it free up engineers to work on things that are more valuable? What will be the impact on the overall output of the organization?

These analyses take time and energy, and some organizations find it easier to buy based on price, which is unfortunate for everyone involved. Engineers often end up using inferior tools that make their jobs harder and their work less rewarding. Organizations put out products that are late or less capable than they could have been. Suppliers end up with lower profits, and thus innovation in automation slows down. This is a losing situation all the way around.

The value of automation (the most important word in EDA!) comes from redirecting engineering effort toward adding value to the chip, rather than just getting through the process. For an organization that designs complex system-on-chip devices to give up on driving its own methodology, instead relying on a supplier of bundled tools because they ostensibly “work together in a flow” or cost less, is potentially a grave mistake. By looking for ways to save time and add more value to their products, in other words investing in unique automation technologies that interoperate based on open standards, these organizations can better satisfy their employees, customers, and investors.

ANALOG TEST FINALLY SUCCUMBS TO INEXORABLE DIGITAL TREND

For decades, our industry has shifted as much analog function into the digital domain as possible. Driven by astonishing scaling reductions, functionality has increased and costs reduced to the point where current consumer gadgets would have been indistinguishable from magic just a few years ago.

This digitizing trend has now extended beyond the design and into the manufacturing process. This promises a currently underexploited opportunity to take manufacturing cost out of semiconductors. But first some background: testing makes up about a fifth of the total cost of manufacturing. Moore’s law inexorably drove dimensions down through the technology nodes for digital, so while wafer-fab costs went up at each node, the cost per transistor went down even faster, giving cheaper die or improving functionality.

Several years ago, it became clear, that test costs were spiraling with transistor count for the digital sections of devices. EDA vendors developed tools to dramatically cut test time and hence cost for digital. Typically these eliminate redundancy in checking digital states and can be Built-In Self-Test (BIST) or loaded onto digital automatic test equipment (ATE).

However, the story is altogether different for Analog and Mixed Signal (AMS). Although analog has not seen the same rise in complexity, test costs have remained stubbornly high, up to 15c/sec for the most advanced analog capability. Test time spent is profit lost. Some high volume AMS chips take seconds and cost $millions to test. It is frustrating when a relatively small analog corner of the chip soaks up vast effort and cost just to develop and run suitable tests on production analog ATE.

Typically digital resources are far more parallel (x32 or x64 and beyond) than their analog counterparts minimizing production bottlenecks and cutting cost per tester site, so clearly testing analog circuitry using only digital resources has cost and throughput attractions. However, by definition, digital resources have limited analog capability such as switching between fixed voltages on digital outputs and checking against a fixed comparator threshold level on the input. One option to exploit this capability is to use BIST. While it is common in digital test and well supported by tools and standards, it is less widely adopted for analog.

BIST has several advantages for analog; greatly simplified ATE by eliminating expensive analog options, offline data processing bottlenecks avoided, parallel testing and the chance for wider circuit coverage of internal circuitry. However, before getting carried away with the benefits, there are significant barriers to universal adoption of BIST in analog. Firstly, the cost gains can be wiped out by the cost of the BIST silicon area. Secondly, while the designer always had to liaise with production test, BIST needs design effort upfront so it must be fast and easy to deploy. A welcome side effect of the latter can be shortened overall time to market. Thirdly, complex analog IP on-chip for BIST circuitry would need its own BIST!

So the characteristics needed for analog BIST to tackle escalating costs of analog test are clear. It must be small, primarily digital with very limited analog circuitry, supported by quick and easy to use EDA tools. A few companies have tried to introduce various exotic methodologies but these failed to gain traction, typically being too theoretical and abstract and inevitably failing the vital production test hurdle. Standards such as 1149.x even attempt to include analog in the boundary scan approach but this has not been universally adopted. A quick Google of ‘Analog EDA BIST’ shows the lack of tools available to meet the demanding requirements. Our company, ATEEDA does offer tools to give Push-Button BIST solutions for analog. These are primarily digital with tiny amounts of analog IP. For example, LinBIST automatically creates the HDL code to put predominantly digital tests on-chip in the smallest number of gates. It also directly targets convertors up to 12 bits with minimal on-chip analog IP giving the comfort of a methodology familiar to test managers. A second tool OptimATE targets a wider range of circuits like regulators and references and signal conditioning circuits and drivers.

My design community: the users

It’s three and a half weeks before DAC—and we, the executive committee and organizer MP Associates—are in the final stages of preparing for the User Track at DAC.  It’s been a joy ride, with some ups and downs.

I was recruited about a year ago to be the Design Community Chair for DAC.  I said I would take the job only if I can re-define what that role means. Andrew Kahng, DAC’s chair, agreed and signed me up.  

The questions began: What is a design community? Does it even exist? And, in what forms? How far does it stretch? And, if these design communities already are associated with established conferences, why would they be interested in connecting with DAC? Can we characterize the profile of a typical “design community member”?

Well, after dwelling on these questions for a few days, looking at years’ worth of survey data from DAC, chatting with members of the DAC Executive Committee and many colleagues designing hardware and software, two ideas crystallized.  First, DAC in the past has had a hard time identifying with a “design community.”  Second, the common characteristic of members of this “design community” was that they “use EDA tools.”

Bingo!  That was it.  The “design community” label is potentially a mismatch: we were really talking about the “EDA Tool Users.” Relief.  At least now we decoded the word “Design” in “Design Community,” and we started talking about “User Community.”  

The quest shifted to find a way of connecting a large community, scattered geographically and topically, yet focused on EDA tool use.  What would bring members of this EDA User Community to DAC?  Certainly not to shop for tools.   The user community is much larger than the folks that typically show up at DAC to visit the exhibit floor.  The question became, what value can DAC provide to the User Community? 

More questions and discussions.  Clearly, users would not be willing to spend the time writing length DAC papers, and the user contributions would not be looked upon with enthusiasm considering the main focus of DAC on algorithmic contributions and methodologies.

So, the User Track was born:  by users, for users, and chosen by users.  We decided on a conference format.  The submissions would be shorter.  The quality had to be high to attract others.  The event would be more inclusive and viewed as a community event to share knowledge and experiences.  The event had to offer networking opportunities.  Submissions must be evaluated using experts in tool use.

It is now eight months later.  We put together a committee of more than 20 super EDA users.  We put the word out that we are looking for submissions –– just one page abstracts.  We received 117 submissions spanning both front and back end design topics.  We accepted about one third as presentations, one third as posters, and one third did not make the quality cut for various reasons. 

I’ve already reviewed some of the presentations and posters that will be made at DAC, and they look GREAT.  Presenters include users from Infineon Technologies, Cisco, TI, Xilinx, ST Microelectronics, Intel, Virtutech, ClueLogic, ST Microelectronics, Samsung, Qualcomm, Intel, Fujitsu, IBM, Sun, and others.

The User Track is this three-day event with 40 presentations running in parallel with regular technical sessions, and a poster session, held Wednesday 1:30-3 p.m., which provides 42 posters.  Did I mention there will be ice cream, too, at the poster session?

Where else can you get such an experience –– the sessions, of course, and not the ice cream?  See you there!