Guest blog: Jay Vleeschhouwer

I’ve known Jay Vleeschhouwer since my early days at Cadence since I somehow ended up with the role of being the technical contact for financial and industry analysts. He has been a research analyst since 1980, has been following the technical software industry for the past two decades. He was most recently a managing director of equity research with Merrill Lynch in New York. Here is his summary of DAC.

DAC 2009: a Wall Street perspective

Industry & technology trends: In the 2009 show, there were a set of new and not-so-new issues (comparing with DAC 2008) that are worth mentioning namely:

  • Analog/mixed-signal, a.k.a. “custom IC”, a vital franchise for CDNS (usually a fourth or more of its revenues, and probably an even higher portion of its earnings, and where SNPS has made its at-long-last entry);
  • Power (the tools and methodology for which have only grown in importance in recent years, although “power analysis & optimization” is relatively small as a discrete EDA reporting category). Power considerations will need to be taken into account throughout the design process (with implications therefore for how the main vendors enable and package their tools). As MENT noted in a product introduction breakfast on July 27th, “system-level optimization” has the biggest impact on power consumption”. Related to that, MENT’s main announcement at the show was of “Vista”, its “architecture-level” power platform.
  • System-level design (representing higher level of abstraction, which is usually a rationale for new growth in EDA). This has now become a $200M+ reporting segment, in which MENT believes it has about a 40% share; and, somewhat more esoterically,
  • 3D “stacking”, a new technique for designing and packaging ICs (a big deal for ST Micro for instance, as it publicly noted).

Industry revenues, product mix, and bookings:

  • According to the latest EDA Consortium (EDAC), EDA license, maintenance, and services revenues were $1.051 billion in 1Q09, down 10%. Not surprisingly, the largest decline was in “license & maintenance”, down 13% to $850 million. The three largest vendors accounted for 70% of the total industry for the quarter, towards the low-end of the 70%-75% range. The difference was largely attributable to the revenue decline at CDNS.
  • According to the EDAC data, the five largest product categories were (remain): IC implementation (11% of industry revenues); PCB (11%); Logic Verification (13%); Analysis tools (8%); Synthesis (6%); RET EDA (5%) and Analog/mixed-signal simulation (5%), or a total of 59%. Of these, the only one that grew in the most recent quarter was RET.
  • For the trailing twelve-months ending 1Q09, the industry revenue was $4.484 billion, down 12%, vs. the trailing-twelve months ending 1Q08, including a 17% decline in license & maintenance revenues for the industry.
  • Over that same period, the combined product bookings of the top three vendors declined ≈35% to about $2.05 billion, mostly because of the plummet at CDNS and the comparison with the large SNPS renewal at Intel in mid-2007. The 2Q data will come out once MENT, LAVA, and SNPS report their July 2009 quarterly results.
  • I’m estimating combined revenues for the top 3 for 2009 of about $3.033 billion (down 5%); combined non-GAAP operating income of about $315 million (or 10% of combined revenues; combined cash flow of under $250 million; and combined bookings of about $2.01 billion, with a weighted average duration of over 3 years.
  • Anecdotally, no customers with whom I met at DAC spoke of planning to increase run-rates, with the preference being apparently to keep even the best-performing suppliers “stable”. Indeed, the disparity between gross bookings and average durations might imply some lower run-rates in some cases when looking at aggregate bookings for the main suppliers.

 Other industry odds-and ends:

With the possible further consolidation of semiconductor companies, or parts thereof, the issue of the transferability of licenses (or the lack thereof specifically) may become an important issue for investors, since there may be instances of some new bookings or re-bookings in some circumstances, depending on scenarios like: Parent company licensee merges with another parent company licensee; Divisional licensee is spun off into a new joint venture entity.

In a keynote address by TSMC’s v.p. of design & technology platforms on “Overcoming the new design complexity barrier”, there were a number of interesting observations and recommendations for the industry (presumably premised too on what would be good for TSMC): the industry is at a “cross-roads” of complexity and affordability; there is a widening gap in terms of the growth of wafers produced and the number of tapeouts (due to growing complexity and cost per design), necessitating a need for more design/manufacturing collaboration, more reuse, and the need for avoidance of redundancies.

At a DAC “management day” panel with senior design executives from Intel, LSI, ST, Infineon, Global Unichip, TI, and Freescale, there was little or no gratuitous EDA-bashing but instead quite reasonable observations about how best to go about the business of designing chips in a timely and economical manner. There were some noteworthy comments and responses on questions having to do with: 1) What they want from their EDA vendors: optimize across different domains (Intel), analog (LSI), chip/package co-design (ST); 2) DFM: unlike design-rule checking DFM is not “black & white”, OPC is a “moving target (ST); very important, developing their own tools (TI). There was also some discussion about (the need for) “software management tools” for design. There is an important difference of scale here as the latter market has order of magnitude more users than are likely to be available in EDA, notwithstanding the extraordinary complexity of chip design. There might finally be a product opportunity here.

Cadence Design Systems. As a very general statement, CDNS’ technical position remains steady, though some customers concurred with the notion that the kind of relative steep improvement we saw from 2001-2006 (pursuant to CDNS’ successful acquisition integration strategy) has run its course. CDNS’ software bookings implosion last year (about -60%) and the further decline this year (down by a further mid-teens percent to under $400 million, which would be, quite unusually, less than MENT’s this year), don’t have much to do with technology (unlike the situation in 1999) so much as semi/industry cyclical reasons and of course the contracts renewal abyss. Given the depths of the recent bookings decline it seems unlikely that CDNS will get back to “normal”, i.e., 2005-2006, annual software bookings levels before 2011, if then.

Mentor Graphics. The main thing Mentor talked about at last year’s DAC was integrating the Calibre physical verification/DFM platform with its Olympus-SoC place & route system (acquired via Sierra Design in 2007). There has since been progress here, which is quite important (see too TSMC’s Reference Flow 10 announcement). For the year, MENT might be able to eke out a small year/year bookings gain, assuming they have a large enough sequential gain in 4Q. The same might be said of SNPS for the year.

Synopsys. In the critical area of IC implementation (one of the largest in all of EDA), SNPS is now seeing the returns from the past 6-7 year path of integrating Avant!’s technology with own, and maturing that combination, e.g., IC Compiler (a large portion of the “core” EDA reported revenues). On the other hand, not s
urprisingly, standalone synthesis has been a declining category for the industry. Granted there are important issues of contact timing, but it’s conceivable that even next year SNPS’ bookings could still be double those of CDNS (underscoring the importance of CDNS’ cost cuts and efforts to improve cash flow).

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