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Category Archives: methodology
3D chips: design tools
One of the open areas for 3D chip design is what the design methodology needs to be and what design tools will be required. A more fundamental issue is going to be the business model to pay for tool development. … Continue reading
Posted in methodology, semiconductor
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3D chips: IBM server
The opening keynote of the 3D conference that I went to was by Subramanian Iyer of IBM. He described work they were doing on fully 3D chips for servers. The approaches I’ve already talked about don’t really work for the … Continue reading
Posted in methodology, semiconductor
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2½D: interposers
There are two classes of true 3D chips which are being developed today. The first is known as 2½D where a so-called silicon interposer is created. The interposer does not contain any active transistors, only interconnect (and perhaps decoupling capacitors), … Continue reading
Posted in methodology, semiconductor
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Going up: 3D ICs and TSVs
This is the first of several posts about 3D ICs. I attended the 3D architectures for semiconductor integration and packaging conference just before Christmas. I learned a lot but I should preface any remarks with the disclaimer that I’m not … Continue reading
Posted in methodology, semiconductor
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Variation-aware Design
Solido has run an interesting survey on variation-aware design. The data is generic and not specific to Solido’s products although you won’t be surprised to know that they have tools in this area. What is variation-aware design? Semiconductor manufacturing is … Continue reading
Posted in methodology, semiconductor
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Carbon
In the latest piece that Jim Hogan and I put together about re-aggregation of value back at the system companies I talked a little bit about Carbon. I got two things wrong, that I’d like to correct here. The first … Continue reading
Posted in eda industry, methodology
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Evolution of design methodology, part II
The second half of the article that Jim Hogan and I wrote on re-aggregation of design at the system companies is now up at EEtimes. The second part of the article looks at the implications for the EDA and IP … Continue reading
Posted in eda industry, methodology
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System re-aggregation
For some time now Jim Hogan and I have been debating whether we are finally on the cusp of one of those design transitions that comes along once every decade or so: the move to gate-level from transistor, the move … Continue reading
Posted in eda industry, methodology
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Polyteda
One startup I did run across that looks interesting is Polyteda. Let me first point out that this is all based simply on talking to them and I’ve not run their tools or done any other diligence. They have a … Continue reading
Posted in eda industry, methodology
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Is it time to start using high-level synthesis?
One big question people have about high-level synthesis (HLS) is whether or not it is ready for mainstream use. In other words, does it really work (yet)? HLS has had a long history starting with products like Synopsys’s Behavioral Compiler … Continue reading
Posted in methodology
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