What is variation-aware design? Semiconductor manufacturing is a statistical process and there are two ways to handle this in the design world. One is to abstract away from the statistical detail into a pass/fail environment with concepts like minimum spacing rules and worst-case transistor timing. Meet the rules and the chip will yield. This is largely what we do in the digital world although with the complexity of modern design rules and the number of process corners that we now need to consider a lot of the complexity of the process is bleeding through anyway. But there is an underlying assumption in this approach that within-die variation is minimal. In fact the very idea of a process corner depends on this: all the n-transistors are at this corner and the p-transistors are at that corner.
But for analog this approach is no longer good enough, instead the design needs to be analyzed in the context of process variation for which the foundry needs to provide variation models. This requires statistical techniques in the tools to take the statistical data from the process and estimate its effect on yield, timing and power. It remains unclear to what extent these approaches will become necessary in the digital world as we move down the process nodes.
Solido had an agency survey several thousand IC designers of which nearly 500 completed the survey, so this is quite a large survey. They are a mixture of management and custom designers (so not digital designers).
The number #1 problem where they felt that advances were needed in tools were variation-aware design (66%) followed by parasitic extraction (48%). Coming up at the rear I don’t think anyone will be surprised that there isn’t a burning desire for major improvements in schematic capture (7%).
Of course the main reason people want variation-aware technology is to improve yield (74%) and avoid respins (64%) which is really just an extreme case of yield improvement! They also wanted to avoid project delays since over half of the groups had missed deadlines or had respins due to variation issues, typically causing a 2 month slip.
When asked which process node people though variation-aware design was important, surprisingly about 10% said that it was already important at 0.18µm, but that number is up to 60% by 65nm and 100% by 22nm.
So this is definitely something the analog guys need to worry about now, and digital need to be aware of. Indeed, Solido is part of the TSMC AMS reference flow (and other companies such as Springsoft and Synopsys have some variation-aware capabilities).