Monthly Archives: January 2011

3D chips: design tools

One of the open areas for 3D chip design is what the design methodology needs to be and what design tools will be required. A more fundamental issue is going to be the business model to pay for tool development. … Continue reading

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3D chips: IBM server

The opening keynote of the 3D conference that I went to was by Subramanian Iyer of IBM. He described work they were doing on fully 3D chips for servers. The approaches I’ve already talked about don’t really work for the … Continue reading

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2½D: interposers

There are two classes of true 3D chips which are being developed today. The first is known as 2½D where a so-called silicon interposer is created. The interposer does not contain any active transistors, only interconnect (and perhaps decoupling capacitors), … Continue reading

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Going up: 3D ICs and TSVs

This is the first of several posts about 3D ICs. I attended the 3D architectures for semiconductor integration and packaging conference just before Christmas. I learned a lot but I should preface any remarks with the disclaimer that I’m not … Continue reading

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Variation-aware Design

Solido has run an interesting survey on variation-aware design. The data is generic and not specific to Solido’s products although you won’t be surprised to know that they have tools in this area. What is variation-aware design? Semiconductor manufacturing is … Continue reading

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Magma’s new P&R and re-building the foundations

One of the important but often unrecognized aspects of engineering is re-building the infrastructure underneath key design tools. Sometimes this gives a new desirable capability but often a lot of the effort is simply to modernize the code base so … Continue reading

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