System re-aggregation

For some time now Jim Hogan and I have been debating whether we are finally on the cusp of one of those design transitions that comes along once every decade or so: the move to gate-level from transistor, the move to synthesis, and so on.

The classic design methodology was built on an assumption that design today is roughly: write the RTL, automatically reduce it to layout, then write a little software for the control microprocessor. But now, for most SoCs, this is completely backwards: 80% or 90% of the design is pre-existing IP. The software load can be enormous but most of it isn’t being written for this specific SoC, it is inherited from earlier designs. This changes the whole nature of design and potentially causes one of those re-jigging of the supply chain and a re-jigging of who realized the most value.

One implication of all of this is that system companies like Apple can design their own systems without having to share so much of the margin with others, as they have done with the iPad A4 chip.

So Jim and I wrote a piece and it is running in EEtimes. I’m not sure how heavily it is going to end up being edited. I’ll put stuff up here that got cut for space reasons. The first part is here.

This entry was posted in eda industry, methodology. Bookmark the permalink.

Comments are closed.