Guest blog: David Hamilton

One area that I don’t know as much about as I feel I should is test. And an area that I know even less about is analog test. David Hamilton is the CEO of ATEEDA, based in an area that I do know lots about (since I did my PhD there) Edinburgh Scotland. His company is working to extend the amount of analog testing that can be done without requiring an analog tester. Of course he’ll be at DAC if you want to find out more. David has has various roles in both academia and industry in both startups like SeFAB to multi-nationals like Honeywell.


For decades, our industry has shifted as much analog function into the digital domain as possible. Driven by astonishing scaling reductions, functionality has increased and costs reduced to the point where current consumer gadgets would have been indistinguishable from magic just a few years ago.

This digitizing trend has now extended beyond the design and into the manufacturing process. This promises a currently underexploited opportunity to take manufacturing cost out of semiconductors. But first some background: testing makes up about a fifth of the total cost of manufacturing. Moore’s law inexorably drove dimensions down through the technology nodes for digital, so while wafer-fab costs went up at each node, the cost per transistor went down even faster, giving cheaper die or improving functionality.

Several years ago, it became clear, that test costs were spiraling with transistor count for the digital sections of devices. EDA vendors developed tools to dramatically cut test time and hence cost for digital. Typically these eliminate redundancy in checking digital states and can be Built-In Self-Test (BIST) or loaded onto digital automatic test equipment (ATE).

However, the story is altogether different for Analog and Mixed Signal (AMS). Although analog has not seen the same rise in complexity, test costs have remained stubbornly high, up to 15c/sec for the most advanced analog capability. Test time spent is profit lost. Some high volume AMS chips take seconds and cost $millions to test. It is frustrating when a relatively small analog corner of the chip soaks up vast effort and cost just to develop and run suitable tests on production analog ATE.

Typically digital resources are far more parallel (x32 or x64 and beyond) than their analog counterparts minimizing production bottlenecks and cutting cost per tester site, so clearly testing analog circuitry using only digital resources has cost and throughput attractions. However, by definition, digital resources have limited analog capability such as switching between fixed voltages on digital outputs and checking against a fixed comparator threshold level on the input. One option to exploit this capability is to use BIST. While it is common in digital test and well supported by tools and standards, it is less widely adopted for analog.

BIST has several advantages for analog; greatly simplified ATE by eliminating expensive analog options, offline data processing bottlenecks avoided, parallel testing and the chance for wider circuit coverage of internal circuitry. However, before getting carried away with the benefits, there are significant barriers to universal adoption of BIST in analog. Firstly, the cost gains can be wiped out by the cost of the BIST silicon area. Secondly, while the designer always had to liaise with production test, BIST needs design effort upfront so it must be fast and easy to deploy. A welcome side effect of the latter can be shortened overall time to market. Thirdly, complex analog IP on-chip for BIST circuitry would need its own BIST!

So the characteristics needed for analog BIST to tackle escalating costs of analog test are clear. It must be small, primarily digital with very limited analog circuitry, supported by quick and easy to use EDA tools. A few companies have tried to introduce various exotic methodologies but these failed to gain traction, typically being too theoretical and abstract and inevitably failing the vital production test hurdle. Standards such as 1149.x even attempt to include analog in the boundary scan approach but this has not been universally adopted. A quick Google of ‘Analog EDA BIST’ shows the lack of tools available to meet the demanding requirements. Our company, ATEEDA does offer tools to give Push-Button BIST solutions for analog. These are primarily digital with tiny amounts of analog IP. For example, LinBIST automatically creates the HDL code to put predominantly digital tests on-chip in the smallest number of gates. It also directly targets convertors up to 12 bits with minimal on-chip analog IP giving the comfort of a methodology familiar to test managers. A second tool OptimATE targets a wider range of circuits like regulators and references and signal conditioning circuits and drivers.

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