IBM didn’t really talk about the design tools needed to design their 3D server chip with the processor on top and the memory underneath. But clearly designing a huge DRAM with holes for TSVs punched through it all over the place and the interconnect full of decoupling capacitors wasn’t done by hand.

One talk was by Vassilios Gerousis from Cadence and Damien Riquet from ST (calling in from France at 2 in the morning his time) about a 2.5D chip they had designed. They were using conventional Cadence tools somewhat unconventionally to get the job done, since it appeared there was no real explicit 3D support .

The first challenge in 3D design is to be able to analyze different approaches for efficiency: routing congestion, TSV density, microbump density, impact on power supply (IR drop etc). Unfortunately this is not straightforward since there are not yet any tools that do this directly: multi-floor floorplanners. The next best is to build the design and be able to analyze it. At this point in the technology there is not a lot of flexibility about what goes on what die since usually the die are different processes (DRAM, analog, RF, CCD etc). But eventually when designs stack multiple die and blocks of IP have several layers where they might reside then automation will presumably be required here just as floorplanning has become essential for regular 2D design.

Cadence/ST created a tool to place the TSVs and the microbumps in regular arrays. Experience has shown that this tends to work better than putting them down randomly since you have some flexibility to design blocks with holes that have more than one place they can be located. They seemed to use a mixture of IC routing and custom design tools to design the interposer. They could then use conventional analysis tools and look at the system as whole from the point of view of power-supply analysis, static timing, thermal effects and so on. OpenAccess served as the link between the various tools, in particular allowing both digital tools (P&R) and custom tools (layout) to work on the same data.

I think the most interesting thing about this is that, at least for a relatively simple design with a non-active silicon interposer, it was possible to get the design done without requiring a complete portfolio of new tools with new support.

The biggest areas of opportunity (and biggest may be a relative term since it is not clear how big the market is for any of these) are floorplanning and general validation of the design (do all microbumps line up, are the voltage levels between die OK and so on). All the big EDA companies have some sort of place & route and floorplanning and might decide to play here. Then there is thermal analysis where a company like Gradient probably has an opportunity to extend their technology into another dimension. General analysis of the electrical aspects of the design could be an opportunity for Apache. Right now the biggest risk for an EDA company is likely to be over-investment rather than missing the boat. 3D ICs are coming but there is not going to be an instantaneous switch with thousands of 3D design starts any time soon, if ever.

Dramatic performance gains from architecture or pushing up clock rate are increasingly unlikely. Moving to a new process node brings performance gains but, of course, is enormously expensive. One of the remaining areas for improving system performance is increasing the size of the cache, and increasing the bandwidth of the cache/processor interface.

Flipping a memory over onto the processor is fine if the processor doesn’t need a heatsink. The highest performance server chips are now dissipating over 150-200W so they need to be on top. In addition, it is almost impossible to distribute the power across a chip like that. At 1V, 200W is 200A which you can’t even get into the chip through conventional wire-bond. And further, the dynamic fluctuations of processor load cause enormous voltage dips which eat up a lot of the potential performance if they are not eliminated.

Using a silicon interposer to connect memory to the processor doesn’t work either since there is just too much long interconnect. The only solution is to build a true 3D chip with the processor on top, the memory underneath and with TSVs going through the memory die to carry all the power and I/O to the processor.

Although SRAM is faster than DRAM, DRAM is so much smaller and dissipates so much less power that in this setup it is preferable, not least because you can have a bigger cache (the memory and processor dice need to be about the same size). The small size wins back enough performance that it is a wash with SRAM.

The picture to the right shows the basic architecture. On the top is the heatsinked processor die. There are no TSVs through the processor die. It is microbumped to attach to the memory die beneath it and to TSVs that go all the way through to carry the 200A of current that it requires direct from the package substrate. The processor/memory microbumps are at at a 50um pitch. The memory die to package bumps are 186um. The memory die has to be thinned in order to get the TSVs all the way through.

In addition, the memory die is choc-a-bloc with decoupling capacitors to reduce transient voltage droops. This allows for increased processor performance without having to give up area on the processor chip for the capacitors since they are in the metal on the memory die. At the keynote, there was a video showing the dramatic difference to the voltage across the chip with and without this approach to supplying power.

The active die themselves do not have any TSVs, only the interposer. This means that the active die can be manufactured without worrying about TSV exclusion zones or threshold shifts. They need to be microbumped of course, since they are not going to be conventionally wire-bonded out. The picture at the head of this post shows (not to scale, of course) the architecture; click on the thumbnail for a larger image.

The image shows two die bonded to a silicon interposer using microbumps. There are metal layers of interconnect on the interposer, and TSVs to get through the interposer substrate to be able to bond with flip chip bumps to the package substrate. Flip-chip bumps are similar to micobumps but are larger and more widely spaced.

So is anyone using this in production yet? It turns out that Xilinx is using this for their Virtex-7 FPGAs. They call the technology “stacked silicon interconnect” and claim that it gives them twice the FPGA capacity at each process node. This is because very large FPGAs only become viable late after process introduction when a lot of yield learning has taken place. Earlier in the lifetime of the process, Xilinx have calculated, it makes more sense to create smaller die and then put several of them on a silicon interposer instead. It ends up cheaper despite the additional cost of the interposer because such a huge die would not yield economic volumes.

The Xilinx interposer consists of 4 layers of 65um metal on a silicon substrate. TSVs through the interposer allow this metal to be connected to the package substrate. Microbumps allow 4 FPGA die to be flipped and connected to the interposer. See the picture to the right. An additional advantage of the interposer is that it makes power distribution across the whole die simpler.

This seems to be the only design in high volume production, at least at the conference this was the example that every speaker seemed to use.

The first thing is the 3D chips do seem to be happening. There are designs in production, there are lots of pilot projects and the ecosystem (in particular, who does what) seems to be starting to fall into place.

The first approach to talk about is flipping one chip and attaching it to the top of another. This is done by creating bonding areas on each chip, growing (usually copper) microbumps to create die-die interconnect at a pitch of approximately 50um. The big user of this technology is in digital camera chips. The CCD image sensor is actually thinned to the point that it is transparent to light and then attached to the image processing chip. The light from the camera lens passes through the silicon to the CCD unobstructed by interconnect etc which is all on the other side of the sensor.

This approach is also used for putting a flipped memory chip onto a logic chip (see picture). It is not well-known, but the Apple A4 chip is built like this, with memory on top of the processor/logic chip. There are now standardization committees working on the pattern of microbumps to use for DRAMs (analagous to standard pinout for DRAMs) so that DRAM from different manufacturers should be interchangeable. Unlike in the picture, the bumps are all towards the center of the die so that the pattern is unaffected by the actual die size which may differ between manufacturers and between different generations of design.

Although this technology is formally 3D, since there are two chips, it doesn’t require any connections through any chips and is a sort of degenerate case.

You probably have heard that the key technology for real 3D chips is the through-silicon-via (TSV). This is a via that goes from the front side of the wafer (typically connecting to one of the lower metal layers) through the wafer and out the back. The TSV is typically about 5-10um across and goes about 8-10 times its width in depth, so 50-100um. A hole is formed into the wafer, lined with an insulator and then filled with copper. Finally the wafer is thinned to expose the backside. Note that this means that the wafer itself ends up 50-100um thick. Silicon is brittle so one of the challenges is handling wafers this thin both in the fab and when they have to be shipped to an assembly house. They need to be glued to some more robust substrate (glass or silicon) and eventually separated again during assembly. The wafer is thinned using CMP (chemical mechanical polishing, similar to how planarization is done between metal layers in a normal semiconductor process) until the TSVs are almost exposed. More silicon is then etched away to reveal the TSVs themselves.

The picture to the right (click for a bigger image) shows Samsung’s approach. FEOL (which, for you designers, means front-end of line which means transistors and is nothing to do with front-end design) is done first. So the transistors are all created. Then the TSVs are formed. Then BEOL (which means back-end of line which means interconnect and is nothing to do with back-end design). After the interconnect is done then the microbumps are created. The wafer is glued to a glass carrier. The back is then ground down, a passivation layer is applied, this is etched to expose the TSVs and then micropads are created. This approach is known as TSVmiddle since the TSVs are formed between transistors and interconnect. There is also TSVfirst (build them before the transistors) and TSVlast (do them last and drill them through all the interconnect as well as the substrate).

There are two design issues with TSVs. First is the exclusion area around them. The via comes up through the active area and usually through some of the metal layers. Due to the details of manufacturing, quite a large area must be left around the TSV so that it can be manufactured without damaging the layers already deposited. The second problem is that the manufacturing process stresses the silicon substrate in a way that can alter the threshold values of transistors anywhere nearby, thus altering the performance of the chip in somewhat unpredictable ways.

What is variation-aware design? Semiconductor manufacturing is a statistical process and there are two ways to handle this in the design world. One is to abstract away from the statistical detail into a pass/fail environment with concepts like minimum spacing rules and worst-case transistor timing. Meet the rules and the chip will yield. This is largely what we do in the digital world although with the complexity of modern design rules and the number of process corners that we now need to consider a lot of the complexity of the process is bleeding through anyway. But there is an underlying assumption in this approach that within-die variation is minimal. In fact the very idea of a process corner depends on this: all the n-transistors are at this corner and the p-transistors are at that corner.

But for analog this approach is no longer good enough, instead the design needs to be analyzed in the context of process variation for which the foundry needs to provide variation models. This requires statistical techniques in the tools to take the statistical data from the process and estimate its effect on yield, timing and power. It remains unclear to what extent these approaches will become necessary in the digital world as we move down the process nodes.

Solido had an agency survey several thousand IC designers of which nearly 500 completed the survey, so this is quite a large survey. They are a mixture of management and custom designers (so not digital designers).

The number #1 problem where they felt that advances were needed in tools were variation-aware design (66%) followed by parasitic extraction (48%). Coming up at the rear I don’t think anyone will be surprised that there isn’t a burning desire for major improvements in schematic capture (7%).

Of course the main reason people want variation-aware technology is to improve yield (74%) and avoid respins (64%) which is really just an extreme case of yield improvement! They also wanted to avoid project delays since over half of the groups had missed deadlines or had respins due to variation issues, typically causing a 2 month slip.

When asked which process node people though variation-aware design was important, surprisingly about 10% said that it was already important at 0.18µm, but that number is up to 60% by 65nm and 100% by 22nm.

So this is definitely something the analog guys need to worry about now, and digital need to be aware of. Indeed, Solido is part of the TSMC AMS reference flow (and other companies such as Springsoft and Synopsys have some variation-aware capabilities).

My gut feel is that a mobile-internet-device will be more like a souped up smartphone than a dumbed down PC, and so Atom will lose to ARM. In fact I think the smartphone and MID markets will converge. Microsoft will lose unless they port to ARM.

Since I wrote that before the debut of the iPad, when lots of people wiser than me were holding the view that netbooks/tablets etc would all need to be Windows-compatible and thus Atom-based to be successful, I think it was a reasonably prescient view.

Yesterday, Bloomberg and the Wall Street Journal reported  that Microsoft is porting a version of Windows to ARM and will debut it at the Consumer Electronics Show in January. Of  course Windows Phone 7 already runs on ARM (specifically the Dragonball processor from Qualcomm) so Microsoft is not a complete stranger to ARM.

The WSJ article says that nothing will be available for two years, which, if true, makes saying anything at CES the ultimate pre-announcement. Indeed, it is a reasonable question to ask whether anyone will care by then. If Microsoft is going to have an ARM-based tablet operating system then I don’t think it can wait that long. Somehow in the mobile, smart-phone and tablet part of the market they never seem to miss an opportunity to miss an opportunity.

The likely loser in all of this is Intel and the winner is ARM and, if they produce something that gains market acceptance, Microsoft. With Windows on ARM, I think that the tablet (iPad-like) market will be largely ARM-based (just like smartphones) and Intel’s Atom processor will have a hard time gaining traction.

The lead investors were Evans and Sutherland (the graphics and flight simulator company in Salt Lake City) and Hambrecht & Quist (one of the earlier VCs).

VLSI had an incredible, especially given its limited size, team of software engineers who put together an entire design system in a relatively short time. We were the first generation of PhDs who had learned the Mead-Conway methodology, so the first generation of computer-scientists rather than electrical engineers, who knew how to design a chip. For several years I think we had clearly the best design tools that you could buy. Of course you had to use VLSI to build your silicon to get your hands on them, which was a good business model when VLSI started out but became less tenable as the DMV (Daisy, Mentor, Valid) got going and promoted the idea of software coming from a 3^rd party EDA industry with libraries as the link to manufacturing. When it was just DMV, largely used for simple gate-arrays, VLSI was still in good shape since more complex designs required more powerful tools. But when ECAD and SDA merged to form Cadence we suddenly had a whole lot more competition. Every semiconductor manufacturer, especially in Japan but even Intel (I bet you’d forgotten they were in ASIC for a while) entered the ASIC business.

Since they didn’t know what they were doing initially, they could only compete on price. In practice, they weren’t very competent for many years. We would often end up bidding on designs where our price (and LSI Logic’s, the other company founded at almost the same time focused on gate-arrays) were twice the Japanese. “Come back when they fail,” we’d say and usually they would.

I think it was Wilf Corrigan, CEO of LSI Logic, who pointed out that the EDA industry stole all the profit from ASIC. They shipped tools that, in the early days at least, really weren’t very good. But the ASIC manufacturers only made money when the design got through so they ended up incurring all the costs of support. If you look at VLSI Technology over the years, it made money some years, lost money other years but it never generated enough cash to grow organically when you took its capital requirements (we had 2 fabs) into account. At one point, as the ultimate vote of no-confidence in the ability to generate profit, VLSI’s book value was less than the cash in the bank.

I joined VLSI about 18 months later. I think my hire date was June 28^th 1982 (and we all got a $100 bonus for July 4^th that year, so not a bad start. $100 was worth something back then). I stayed for 16 years eventually sawing off the branch I was sitting on. By then I was running Compass and we were acquired by Avant! I stayed there for 8 hours after the deal finally closed, resigning on a Friday afternoon and starting at Ambit on Monday morning. Good decision.

The non-Compass part of VLSI was eventually acquired by Philips Semiconductors (now NXP) in a hostile takeover in 1999 for $1B.

By some measures, VLSI was a big success: we invented an industry, pioneered various design tools, were successful in PC chipsets, early into wireless and grew from nothing to a $600M (I think) business. But the stock price never went anywhere in 15 years, spending most of its time lingering in the $11 to $15 range. In fact from my personal financial point of view, the most important event was the 1987 stock market crash when all our options were repriced to $4. So once the stock went back to its usual range there was a nice profit.

But I learned an incredible amount about silicon, software development, management. Compared to most people in EDA I like to say I have silicon in my veins. I’m often disturbed by how little about semiconductors EDA people know. It was a great ride.

As you probably know, eSilicon is a fabless ASIC company. They operate like an ASIC company and not like a design house although they do provide design services too, just like any ASIC company. But their business model is not to do the design and hand it to you, and then have you go and get it manufactured. They manage the entire manufacturing process and deliver you packaged, tested parts just as if they had their own fab. Primarily they use TSMC for manufacturing. But they are completely independent. Indeed I met with them at the Global Foundries technology conference.

They have been in existence for 10 years, created soon after Jack Harding was pushed out as CEO of Cadence. Today they are about 330 people with and expect this financial year’s revenues to come in at around $130M. That is larger than I expected in both headcount and revenue. Of course because the manufacturing revenues flow through their P&L you have to look at them as a manufacturing company and not a service company. Like any manufacturing company they have significant CoGS (cost of good sold, basically what they pay TSMC and their other suppliers to build the parts).

Their business actually splits into 3 parts: designing basic gates, IP and operational outsourcing.

Basic gates is largely taking RTL, doing all the synthesis, place and route and then taping out the chip. This is the basic ASIC business of having the customer do the front-end part of the design and then taking over to do the back-end. As well as doing design in the US, eSilicon acquired Sycon with an engineering organization in Romania.

In addition they have their own portfolio of IP that they will license you. Much of this is licensed from 3rd parties but in addtiona eSilicon aquired Silicon Design Solutions in Vietnam where memory IP is developed today.

The newest part of their business is operational outsourcing. Small fabless semiconductor companies who do their own design often have little expertise in operational management of a semiconductor supply chain. Typically for these designs eSilicon does not do the design at all, the customer does that. But then eSilicon takes over and manages all the manufacturing using the fact that they have relationships with foundries, packaging houses, test houses and have operational specialists who do this every day. Since they have a 10 year track record at doing this successfully, it is a low risk solution for a company to let eSilicon take over.

I’ve written before about how VLSI Technology, one of the inventors of ASIC, would probably have been more successful to have split into an EDA company and a fabless semiconductor company (Cadence and eSilicon) rather that keeping a fab along with the financing and technology development challenges that it posed. Of course this is more a case of Monday morning quarterbacking since this was certainly not obvious at the time when wafer foundries were not really seen as real businesses, more a way of unloaded excess capacity (VLSI even did foundry business at various times in its life).

But it’s nice to see eSilicon being successful and vindicating that idea.

Just in case you don’t remember who Global Foundries are, they are the old manufacturing arm of AMD which was spun out (partially, AMD still kept a share) and purchased by ATIC, a financial group based in Abu Dhabi. They since went on to purchase Singapore-based Chartered Semiconductor.

The first thing that surprised me about the conference was just how many people there were there, I’d estimate well over a thousand. There is clearly a lot of interest in the existence of a strong competitor to TSMC and Global seems to be the most likely candidate. They claim to be in the middle of the fastest volume process ramp for 40/45nm, using AMD’s microprocessor line as a yield driver.

Indeed, AMD announced two new microprocessors manufactured using Gobal’s 45nm node: Bulldozer and Bobcat.  Bulldozer is oriented to performance and scalability targeted at server farms. Bobcat is tailed for small die-size, low power targeted to portable devices. Both cores are complete re-designs.

A lot of Global’s strategy became clear from the presentations. They are clearly planning to be very aggressive at winning business at the 28nm and 22nm nodes. In fact I would go as far as to say they are “must win.” Abu-Dhabi may have deep pockets and are certainly investing freely, but eventually they will want to see serious profits coming back their way. They are investing a huge amount in process development and are building a big new fab (fab8) in Saratoga NY. They claim their process, which is high-K metal gate (HKMG) gate-first, is 15% more efficient that gate-last processes (take that, TSMC). But I’m not nearly enough of a process expert to have my own opinion. They are using ARM Cortex-A9 as a process driver, which they have already taped out. I’m guessing that because it is synthesizable, it is much easier to use as a process driver than an AMD design, which would otherwise be the expected choice.

Greg Bartlett, senior VP Technology and R&D, had some interesting perspective on what are the drivers of progress. Until about 60nm progress was almost all about improving lithography. That’s not to say that there wasn’t other development (copper interconnect, Hi-K dielectric etc) but the big breakthroughs were things like immersion lithography and double-patterning. Then a second driver came online, materials integration: strained silicon, HKMG. And from 32nm onwards 3D integration is going to be a 3^rd big driver of value, driving density higher (although there are still some major power challenges to be addressed).

I was in a couple of meetings at DAC about 3D. One of the issues is the scale of the problem. There are a lot of separate problems that need to be solved from floorplanning (with multiple floors), simulating the entire stack of different interconnects, power and thermal analysis (and it’s not all bad, sometimes putting one die on top of another smoothes out hotspots since every die is also a heatsink), process issues (bumping etc) and all need to be solved pretty much simultaneously for it to be useful. It reminds me a bit of tape-automated bonding (TAB) which took much longer to come online than anyone expected for similar reasons. It’s hard to boil an ocean.

Reading between the lines, this looks like it is all going to be ARM-based. The first release is optimized for ARM’s Cortex-A family, the quote in the release is from ARM’s VP of corporate development, and all the companies in the announcement have significant investment in ARM-based products.

Traditionally Linux has been developed to run on Intel processors. It was originally “Unix for the PC.” Because of architectural compatibility this meant that Linux ran on Intel’s Atom core too. This consortium is going to try to make sure that Linux runs even better on ARM-based platforms. None of these semiconductor manufacturers can ship products for smartphones and netbooks without a good Linux release. On the other hand, by pooling their resources they will end up with a software stack at a fairly low cost and zero marginal cost. They are not going to compete on the OS level of the software stack.

But therein lies a problem for them. If the software stack is the same for everyone, it is very hard to differentiate much on the hardware level underneath either. Yes, performance and power consumption will be differentiators but using the same ARM cores on similar silicon means the differences will be minor. Which leaves price.

First Apple and then Google’s strategy in wireless has been to put all the differentiation in application software and industrial design, reduce the wireless network operators to dumb pipes (no more walled gardens) and reduce the hardware suppliers to commodities (all Android phones are pretty much the same).

On the same day, AT&T announced that it was ending unlimited data plans that has been one of the big drivers of mobile Internet. But they obviously don’t think that they are making enough money as a dumb pipe to justify the infrastructure costs. Apparently a tiny handful of users generate almost half the data traffic, although the limits of 2 GB seem unnecessarily low if there really are such a small number of superusers who are overloading the network.

So this is the future: commodity chips going into commodity phones running a commodity operating system on a commodity wireless network. The money is in what you do with your phone, just as it is in the non-mobile world.

I think that for the time being, Apple will be able to command a higher price point and some differentiation but their costs will be much higher and that might eventually become a big problem. But in the meantime they will make all the money.