Guest blog: Mike Smayling

Mike SmaylingToday’s guest blog is from Mike Smayling, who is the senior VP product technology at Tela Innovations. He has a background in both the semiconductor industry at Texas Instruments, and semiconductor equipment at Applied Materials. In a couple of earlier entries I looked at the implications of lithography on design, and on how a whole spectrum of DFM companies were launched and (largely) died. But when we get down to 32nm and below the rules for what we can put on masks will start to change significantly or there is simply no way to print them during lithography. Mike explains the background and a little of the Tela approach.

Gridded Design Rules with Lines and Cuts: the Shape of Things to Come

After over 50 years of lateral and vertical scaling of integrated circuit dimensions, we are approaching a fork in the roadmap. We need to choose between design “business as usual” or a new design style which gives an important degree-of-freedom to the overall patterning optimization problem.

The root cause of the current problem is illustrated by the Rayleigh equation,

Half-Pitch = k1 · wavelength / numerical-aperture or R = k1 l/NA.

The coefficient k1 is a fitting factor; lower k1 means more difficult lithography. With l/NA limited to 143nm, lower k1 will be the focus for reducing feature sizes.

Conventional IC layout uses “2D” shapes with bends, jogs, and other features which don’t get through an optical scanner “low pass filter.” The random shapes used to create random logic functions do not allow optimizing the photolithography systems. Instead, they force a “lowest-common-denominator” approach which ends up not getting the best usage of increasingly costly equipment.

There have been countless DFM panel sessions at numerous conferences discussing the problem. Experts have pointed out the growing number of design rules needed to communicate capabilities from the wafer fab to the design team. There have been other layers of design rules added, such as “recommended rules” and “restricted rules,” which attempt to either relax dimensions to improve yield or to restrict pattern-dependent combinations of dimensions to avoid potential yield problems.

Numerous DFM startups appeared with tools to predict “hot spots” or locations which were prone to necking or bridging problems within the process window. Later tools were able to give repair recommendations or even fix problems. Unfortunately, most of the tools had claims like “we fix over 90% of your hotspots.”

An interesting approach to improving the overall patterning system has been SMO (source – mask optimization). This involves trying different illuminator shapes, like annular, dipole, or cross-pole, to address the source issue, and different OPC (optical proximity correction) approaches to address the mask issue. Very complex solutions can be found using computational lithography, in which both the source and the mask can be pixilated with different intensity/polarization and transmission at each pixel. Of course, there are issues with the illuminator stability and qualification, and issues with mask manufacture and inspection.

The other tine of the fork leads away from CDR (complex design rules) toward GDR (gridded design rules). GDR layouts using “1D” lines can be fabricated at lower k1 values than complex 2D layouts. The Tela Canvas is a GDR approach which has been shown to give competitive area at lower dimensional variability using standard patterning.

An important benefit of GDR will be realized when SMO is extended to include design rules in the optimization. This is possible because GDR involves a small set of rules like width, space, and end-gap for each line level, and width and space for hole levels. Large regions of design space can be mapped out to demonstrate where hotspots are, and rules can be set which avoid problem regions.

An additional benefit of GDR will come from improving the ability of wafer fabs to do failure analysis. A harsh reality for DFM companies is that wafer fabs are ultimately responsible for yield. This means that anything that can be done from the design side to simplify incoming patterns and variations in patterns will ultimately improve yield.

For advanced technology nodes, like 32nm and below, it is straightforward to extend GDR by using “lines and cuts.” In this approach, a layout is decomposed into two patterns: one for straight lines, the other for cuts which define where breaks are created in the final lines. Lines and cuts are already common in the gate level of 45nm CMOS logic, where it adds value in the SRAM bit cell by reducing the tip-to-tip gate spacing. Recent examples of 22nm half-pitch patterns done with lines and cuts show that there is no patterning barrier down to 16nm logic dimensions.

One dimensional layoutLines and cuts allow each patterning system to be separately optimized. SMO can be effective to get better use from lithography systems for lines, as is done with NAND Flash memories today. The cut patterns can also be optimized for optical lithography, or with relatively low pattern densities, could be handled by multiple-e-beam systems.

Anyone who has done classical filter design knows that cancelling poles and zeros is easy in principle but difficult in practice. The complex path will lead to a more costly solution as 2D patterning systems are used at ultra-low k1 values. The 1D Tela path stays with relatively simple solutions today, and delays the need for complex SMO for 2-3 generations.

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