I see a fair number of EDA startups. Most of them have some potentially innovative technology that solves a problem that is getting or going to get worse at future process nodes. But it is really hard to assess whether the technology works well, whether it will work on the type of designs that will be done in the future, and whether the approach will turn out to form a sizeable market. At the last few jobs I did I had to work as a consultant for a time before I could even assess whether the technology was good enough to want to sign onto the company.
Sometimes, though, I see a company that is instantly interesting. One such company I talked to recently is Oasys, where I spend an interesting hour or two with Paul van Besouw, the CEO. A disclosure: all the founders of Oasys worked for me at Ambit, although I haven’t done any work for them and don’t own any stock. But I’d like to.
Oasys has, to my mind, have developed a true next generation approach to synthesis. All synthesis tools to date, Synopsys Design Compiler and the equivalents, along with all the FPGA synthesis tools, take the same basic approach. The RTL is read and analyzed into a control-dataflow graph. This is naïvely synthesized into essentially a network of nand gates with the correct functionality. Optimization then takes place at the gate level, perhaps involving some gate-level placement so that physical information is taken into account during optimization. The algorithms can be clever but they are limited because they are operating at the gate level. If the netlist is several million gates then it is bound to require a huge amount of memory and bound to be slow. Eventually the optimization achieves the best result it can, it is written out along with placement information and then the place and route tools take over.
Oasys takes a different approach. They take the view that optimization should start at the RTL level, on the usual rationale that higher-level tradeoffs bring bigger changes, and so getting it right at the RTL level saves a lot of time-consuming small-scale gate-level optimization that might not even get there due to the usual local minimum and other problems.
However, in a modern process there is little point in trying to do any timing without first having placement, and so it is necessary to start to place the hierarchical blocks and then the RTL level objects such as registers and adders even before they are reduced to gates. Most of the effort goes at this level, and only right at the end of the process is the netlist finally reduced to placed gates.
So what is the result of this? The first result is that it is tens of times faster. The Sun Ultrasparc open source core, which is a day or so to synthesize using current tools, completed while I talked to Paul van Besouw, the CEO, in about 20 minutes, maybe 30 times faster, running on an old laptop. I didn’t measure it directly, but the amount of memory required was about one hundredth of what was required by Design Compiler which would never have been able to handle a design of such as size on a regular laptop. People who have used the tool on real designs report that it produces equal or better QoR (quality of results, usually some measure of total or maximum negative slack). I’m not one of those people, of course, so your mileage may vary.
The good news doesn’t even stop there. The place and route is faster than before because the placement is already so good (it is the dirty secret of place and route tools that it’s all about the placement) and the good timing results are not lost during physical design.
Today people have to break down designs in order to get the design through synthesis in a reasonable time. Unless the blocks correspond to physical blocks in the eventual hierarchical layout it is not really even possible to do realistic timing at this point, that needs to be left for the place and route tool to tackle. Oasys’s RealTime Designer can just gulp down the whole design and simultaneously optimize everything, leaving the place and route tool with a little bit of cleanup and the detailed routing to complete.