I spent part of last Tuesday at the Cadence mixed-signal workshop. I went mainly out of interest to see how things had progressed since I worked at Cadence. I had been put in charge of what we called the Superchip project, which was actually integrating together the custom design and the digital synthesis, place & route design to get them into a single design environment. The heart of the problem was to get both systems onto a single database for mixed signal design. This turned out to be immensely complicated since the basic semantics of the two design databases were so different, and nobody in the company had a deep understanding of both of them.
Now, many years later, that work seems to have largely been achieved, but in about 5 times as long as we originally planned.
I thought the most interesting thing was a summary of just how much mixed-signal is impacting design cost. Over 50% of re-spins at 65nm are due to mixed-signal and each respin costs $5-10M and takes 6-8 weeks. Mixed-signal chips typically take 4-5 respins to get right. That is a huge cost both in direct dollars ($20M-50M) and in time (4-5 respins of 6-8 weeks is upwards of 6 months).
The level of mixed-signal effort and the expertise required is also increasing significantly. It now takes 50% of the effort for 10% of the transistors. The basic technology for integration and verification is still too fragmented and there is a lot of ad hoc work to tie together things like self-test.
The next area of difficulty is packaging. It severely impacts device performance due to the package parasitics. The lack of good optimization tools for the chip/package interface makes for lower performance and further drives package costs up.