Around the Imax with EDA360

e360.jpgCadence had a big announcement at the Embedded Systems Conference this week. Actually, not at the conference (I don’t think they even have a booth) but in the Imax theater in the Tech Museum (and, on another topic, are they ever going to update any of the exhibits in the Tech Museum?) Yes, Cadence and embedded systems are not things you usually think of together. However, they announced their vision for the future of EDA, which they call EDA360.

The EDA360 vision is actually pretty close to a lot of the themes that I’ve talked about on this blog: the increasing irrelevance of chip design in the much bigger universe of electronic system design, the growing importance of software and so on.

For Cadence to move up to the system design level they lack a number of things. Firstly, they have no virtual platform technology to provide to the software developers. They do have high level synthesis, the CtoSilicon (curiously Synopsys is the one that doesn’t but I expect them to buy one of the existing companies, if not immediately then whenever it is clear who the winner in the space is). They don’t have FPGA synthesis, which is a problem since most designs are FPGAs. And they don’t have anything for the embedded software space. Of the big EDA companies, only Mentor has although they’ve struggled to grow it as much as they’d like.

Cadence also announced a couple of specific programs. The first is an attempt to plug the virtual palatform hole: a partnership with Wind River around Simics (the software from Virtutech that Intel/Wind River acquired earlier this year). If that’s Cadence’s strategy I’m not sure why they didn’t buy Virtutech (reputedly they tried to by CoWare for nearly $100M and Virtutech sold for only $45M).

The other thing they announced was the Cadence Verification Computing Platform. I’m not 100% sure what this is. I think it is the latest product in the Quickturn line of accelerators and there was certainly an impressive looking box among the wine and appetizers. But in an attempt to position this as the second significant step in EDA360 they layered it with so much marketing smoke that you couldn’t see through to the mirrors.

EDA360 is a four-legged stool. The basic premise is that there is a tectonic shift going on in the semiconductor industry. Instead of just delivering systems they need to deliver a complete value stack with a lot of software too. I still think that one of the big challenges there is that semiconductor companies only know how to sell margined up square metres of silicon, and treat software as a marketing expense. That was fine when there was only a bit of it, but when there is more engineering effort in the software than the chip, and a lot of the differentiation is in the software then this is inappropriate. So leg number one of EDA360 is that there needs to be a shift towards focusing semiconductor companies more on integrating hardware and software IP, and less on design creation, in order to get their profitability up.

The second leg is application-driven system realization. I think this is close to what I call software signoff. Instead of developing a chip and then worrying about writing some software to run on it, conceptually it is the other way around. The software comes first and the only purpose of the hardware (which may or may not be a chip) is to run it fast enough, and at low enough power, and provide the required interfaces to the outside world (wireless, 3G, optical etc). From a practical point of view, though, it is not enough just to provide the hardware since a lot of software may well be provided by the end-user. So the software ecosystem must be fed with drivers, development kits, simulators and so on. Think of what Apple provides for iPhone developers.

The third leg is software-aware SoC realization. I think this is really a subset of the second leg for designs where the system is actually (mostly anyway) a single chip. SoC design, of course, is Cadence’s comfort zone. But tying into software really increases the importance of transaction-level modeling, virtual platforms, and generally realizing that the software is often master over the chip design requirements.

The fourth and final leg of the EDA360 stool is silicon realization. This needs to be made more efficient by pushing up the level of abstraction, building appropriate links up to the software world (especially for power consideration) and so on. This is sustaining and updating the existing product line in a way that Cadence would have had to do anyway.

I think Cadence is trying to go in the right direction and it will be interesting to see what specific things they do to flesh out the vision with real products. One of the big challenges is that their focus and revenue comes mostly from IC design, moving up into the system space is disruptive (in the Innovator’s Dilemma sense). I think success would be when Cadence is making serious money selling to people who do no chip design, just build systems with FPGAs, boards and standard products (plus lots of software). The challenges are largely on the business side rather than the technology side. As the old joke about a guy asking for directions in rural Ireland goes, “If I were you, I wouldn’t start from here.” It’s not clear whether Cadence’s IC heritage is the right base upon which to build this vision.

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