So what was the theme of DAC this year? Two things stood out for me: one is that the big EDA companies are getting serious about doing design at a higher level. I think we need a new name for this since ESL tends to focus on IC design, whereas the underlying message is that moving to the higher level is about designing electronic systems including their software, not largely about chip design.Mentor has had a portfolio in this area for years. Synopsys has been vacuuming up companies at this level: VaST, CoWare, Synfora, Virage.
Cadence has put their EDA360 stake in the ground and also acquired Denali. I think the price is insane. John Bruggeman asked me whether I thought Virage or Denali was the better buy and I had to say Virage. I find it hard to believe that there is a huge untapped reservoir of demand for Denali’s products that the Cadence sales-force will unlock whereas I think the Virage product line can be leveraged by the Synopsys salesforce, especially given the rest of their IP portfolio. The interesting thing about the Virage acquisition is what, if anything, it does to affect their relationship with ARM since it now puts them squarely in competition with ARM for the old Artisan part of their product line, and, with ARC, at least obliquely in competition with them in the microprocessor space. But they both need each other so they probably just have to live with it.
EDA is still somewhat stuck in an outmoded style of design that assumes the chips are designed from scratch and then someone writes some software to run on them. In fact much of the software already exists: software generations are 10 times as long as chip generations, and chip design is increasingly about IP assembly rather than efficient design from scratch. I continue to believe that this block-level is an interesting choke point, with the potential to generate a virtual platform for the software developers and testers, and the potential to turn the design rapidly into an FPGA or SoC. But the tools don’t yet exist.
One other thing that is broken is clearly the funding model. There are very few new startups at DAC since VCs know that this is simply not an interesting industry: not growing, no IPOs and so on. Lucio Lanza, in his panel session, was pushing the notion that EDA software is going to become free, and open-source, and EDA companies need to make the transition to services like IBM. I don’t buy it. I don’t believe that open source will really work in EDA, at least at the leading edge, because open source has always proved poor at innovating products that require getting the specification right (and where the programmer is not the user). That’s the reason there are no good open source games. It is too hard to predict what will be a hit, and when a hit does come along it is too late to create an open-source clone. But EDA is a bit like that at the leading edge, with new process generations coming along. By the time you know the features you need in a tool it is too late to launch an open source project to clone it.
I was on a roundtable with Riko Radojcic of Qualcomm, and he pointed out that the big problems now are things like chip-package co-design, or software-power integration or complete 3-D design analysis, all areas that are probably too big for a traditional startup with an engineering team of perhaps 10 people max. But historically discontinuous innovation has always come from startups rather than the big established companies with less than a handful of exceptions. If the problems are too big, and/or the startups aren’t being funded, it’s not clear where the discontinuous innovation will come from.
I happened to be involved in couple of events where we talked a lot about 3D chip design: stacked die using various through silicon via (TSV) approaches to make the vertical connections. Javelin were working on this before their demise and Atrenta seemed to have picked the baton up off the ground. They had a demo working with imec and Qualcomm, along with AutoESL and Atrenta to demonstrate a 3D design flow, or rather the prototype for a design flow. What Riko calls pathfinding (hey, that’s very green recycling the name of the old Compass router) developing the outline for how to use a technology a couple of years before it is actually available. Qualcomm expect to do 3D production chips in 2012-3; so far they have only done test chips.
Of the companies I was working with, Oasys and Tuscany, both had essentially full suites the whole time.So although DAC felt quieter (see those extra-wide aisles) the key people seemed to be there. It remains a weird show, largely put on for the key purchasers in a few dozen companies.
Oasys had irreverent videos taking off the “I’m a Mac, I’m a PC” ads. Synopsys people (even Aart) would sneak by trying to get a peek without actually blatantly standing there and looking. They are pretty funny, and are now up on the Oasys website.
Next year, DAC is in San Diego from June 5-10th.