Which are the interesting areas of EDA right now? As a general rule, I think that the answer is "the ends" which today means the architectural level and the transistor layout level. There will always be some interesting areas in between too, of course, but the main flow from RTL to layout along with the respective verification methodologies are largely solved and so there is limited scope for major innovation.
The transistor layout level is really about the interface between EDA and semiconductor process. There are two things that make it a challenge. One is the changes in lithography which have complex effects on what can and cannot be put on a mask in a form that will print. The second is that EDA largely operates with a pass/fail model, whereas process is actually statistical. It is like the way we regard signals as digital, which works most of the time except occasionally the analog nature of signals breaks through when a signal changes too slowly or some other unusual effect causes the illusion to break down.
The architectural level is where chips and software intersect. Chip design people tend to think of the architectural level as somewhere that the system designers make a start on chip design. But a better way is to think of the software as a specification of the system and the only purpose of the chip is to run the software. Why would you not just run code on one of the on-chip microprocessors? Only for 3 reasons: to do so would be too slow, to do so would consume too much power, or you can’t do it in software without a special peripheral (for example, analog). Increasingly SoCs are processors, buses and memory, along with specialized IP blocks (which may themselves contain processors) for performance, power or analog reasons.
The big challenge in a system like that is getting the software right. I keep waiting for the virtual platform concept to really take off, since I’m convinced it is a better way to do development. Look at all the complaints about inaccuracy in the iPhone simulator (since it just cross-compiles) or the difficulty of doing performance analysis since you need to do it on the real phone. SoCs are much more complicated since typically they have multiple processors with different architectures since code running on (say) a Tensilica or ARC processor optimized for audio processing has very different characteristics from running the same code on an embedded PowerPC.
But the block diagram of the virtual platform is actually the chip specification as well.
I think that moving up to the architectural level should focus on this virtual platform level. Like Goldilock’s porridge, it is just right. It contains just the right amount of detail. By using the platform to run code, the software development can be done much more productively. By using the virtual platform as a specification on how to integrate all the processors and IP, the chip can be created. It is like using RTL but at a much higher level. With RTL we can simulate it to get the chip functionality right, and we can use it as an input to a (fairly) automatic process to create the silicon. The virtual platform has the potential to play this role.
That would mean that the architectural virtual platform level would become a handoff between the engineers creating the systems and the lower level implementation. With synthesis timing was the unifying thread across the handoff; with this sort of architectural handoff it is communication within the software, which interacts with timing, functionality and power, of course, making it possible to optimize the SoC implementation.
People looking at ESL only as behavioral synthesis I think are missing the point. It is like software engineers arguing about details of language syntax. The hard problems are all about writing large scale software or integrating dozens (or even hundreds) of IP blocks quickly and getting the software working. Yes, behavioral synthesis has its place as the ultimate in “inlining” functions with extremely high performance and low power, just as in the software world people occasionally hand craft assembly code and sometimes measure cache hit-rates.
As Yoshihito Kondo, general manager of Sony’s design platform division said, "We don’t want our engineers writing Verilog, we want them inventing concepts and transferring them into silicon and software using automated processes."
That one sentence is a vision for what EDA should aim to become.