Another look at internal development

I’ve talked before about internal development, by which I mean semiconductor companies developing their own tools. I just don’t think that it is going to happen in a big way.

In the early 1980s VLSI design techniques were being disseminated outside a handful of semiconductor companies where the priestly knowledge had previously been secreted. VLSI Technology and LSI Logic (primarily) invented ASIC design, whereby customers did part of the design and the semiconductor company (we called them foundries then, but they were not exactly the same as what we call a foundry today) did the rest. A lot of design tool development was internal. There was a good reason for that, namely that there was no 3rd party EDA industry providing the necessary tools, and so no tools meant no product to fill the fab. Remember that if you have a fab you are like an hotel; every wafer start slot with no actual wafer to start is like a plane with an empty seat. Once the slot has passed or the plane takes off, it’s gone for ever.

So VLSI Technology and LSI Logic (and HP, Intel, TI and everyone else) had a large amount of internal CAD. It was differentiation to some extent, and there wasn’t really an alternative. The CAD teams were staffed with top rate engineers, many of them M.Sc. and Ph.D. students from the first cohort of people from universities starting to teach and research VLSI design.

Then came the first wave of EDA companies, the DMV—Daisy, Mentor and Valid. They provided systems for doing some front end design, basically schematic capture and simulation. The standard ASIC methodology was to do design to netlist, ship the netlist to the semiconductor vendor who would do place and route (either as a standard-cell design or a gate-array) and provide back annotation of capacitance values (we didn’t worry about resistance back then, timing was dominated by capacitance) for resimulation and signoff.

This design flow didn’t work very well at first. Wilf Corrigan, CEO of LSI Logic famously complained that the EDA industry took all the profit from ASIC. Customers would buy tools but the semiconductor company would only get their money once a design could get through the flow. So much of the heavy lifting to mature the flows and make them workable was done by the semiconductor companies not the EDA companies. The next generation of EDA companies was SDA and ECAD who merged to form Cadence (this was long before Synopsys). The Japanese semiconductor companies adopted 3rd party EDA vigorously, since they had very limited internal development and this allowed them to get into the new markets that ASIC was opening up.

The writing was on the wall for internal EDA, at least in the long term.

So the EDA part of the business split into an external part, the EDA industry, and an internal part, the CAD groups. By and large the CAD groups were training grounds for entry level engineers, some engineers with deep design experience and, usually, first rate management (often drafted in from the design side of the company to keep the internal politics calm). They knew how to use tools but not how to create them. The internal tool developers migrated from the semiconductor companies into the EDA companies.

The two exceptions to this, companies that kept large internal development groups, were Intel and IBM who still, to this day, develop significant amounts of EDA software for their own internal use. But it is very expensive to do this, and even they don’t know how useful it is. I once asked someone in Intel’s Design Technology (their internal CAD/development group) whether their routers were better than the EDA industries. He admitted they didn’t have a clue; they had no bandwidth to even take a look at what was available externally.

So I don’t see internal development being a major force since the economics don’t work very well. However, that could change with consolidation of both EDA and semiconductor companies, and especially if a semiconductor company jump-started internal development by acquiring one or more EDA companies.

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