Today’s guest blog is by Phil Moorby who back in the 1980s at Gateway Design Automation was the inventor of the Verilog language, for which he was given the prestigious Kauffman award in 2006. Gateway was, of course, acquired by Cadence. Today, Phil is CTO of Sigmatix Inc.
Verilog: A Name for Getting the Job Done
Verilog. Verification and Logic. Sometimes it’s all in the name.
When we set about architecting a language for next generation IC design at Gateway Design Systems in the 1980s, our overriding principle was “simple is powerful.” We wanted to create a language that an engineer could learn quickly and use easily, that covered exactly the necessary tasks and nothing more, that needed no relearning after a pause in use.
The success and endurance of Verilog is testament to this foundation. The original design considered the requirements of fast gate simulation, synthesis, timing analysis and test. Later, the language supported more advanced timing directives, and other necessary features. During this growth, it always retained its elegance-of-use, which ensured its survival and, eventually, its adoption as the industry standard, even as the public domain VHDL language gained prominence.
From the outset, the original Gateway team primarily targeted synthesis and verification (simulation only with behavioral directed testbenches). We soon partnered with another up-and-coming, small company, Synopsys, to ensure a synthesis path for Verilog, and engineers quickly realized the power of the approach. Fast gate level simulation was another key feature and the gate level representation of the language bore this out.
One of the powerful reasons for Verilog’s staying power was its sign-off status among numerous ASIC vendors. It was Motorola who first recognized the potential of Verilog-XL as a sign-off simulator, and the inclusion of timing capabilities and gate modeling methods to meet stringent constraints made this possible. Widespread ASIC sign-off for Verilog imposed a significant barrier to entry for other simulators and languages of the time.
In 1989, Cadence Design Systems acquired Gateway and the rights to the still proprietary Verilog language. The public domain VHDL language was gaining momentum with the backing of other large EDA Vendors, including Synopsys, several influential systems companies, and some government bodies. There is a lesson here regarding the timing of introducing a proprietary language into the public domain and its business impact. It was clear that VHDL gained prominence due to its open standard nature. The battle lines were drawn between the big EDA Vendors and, inevitably in 1991, the Verilog language was donated to the newly formed Open Verilog International (OVI), now part of Accelera, and released into the public domain. One could argue that this has lead to healthy and productive competition.
A key component that aided the creation of the language was a deep consideration of the problem for which it was designed and how it was to be used. It was more important to be able to create a couple of lines of code and immediately run the simulator, and not have to spend days planning configurations and writing superfluous statements before getting to the design functionality.
This core directive, carried over to Verilog 2.0 and Co-Design’s Superlog language, seems to have been diluted in the latest incarnation of the language, SystemVerilog. The driving requirement behind SystemVerilog was to address the compelling demand to solve the verification problem while raising design abstraction, the major verification components being formal analysis and testbench generation.
Although the principles behind the language requirements are sound, the fact that it is designed to be used by engineers from widely differing disciplines has driven it to become, essentially, a collection of several languages. The simplistic sensibilities of the original Verilog have given way to an overarching family of languages, rendering it somewhat unwieldy. I would claim that an engineer needs to think in one language to drive a successful design.
Take the analogy with the European Union and its three primary working languages: English, German and French. Consider the subtle ambiguities that arise when important details need to be translated precisely and communicated between EU members. Some would argue that this has slowed down progress and added layers of bureaucracy. While this may be necessary when bringing together government bodies, the approach is questionable for a design system. Not just talking, but actually thinking in the same language, accelerates progress in many fields.
An interesting aspect of SystemVerilog is its name. Arguably, the one component not represented in the language family is systems. Maybe it is time EDA technologists stop designing overly complex languages and methodologies, and return to what made early solutions successful, a single minded focus on the problem.
Take ESL. The notion of Electronic System Level design suggests that what is required to provide effective systems methodologies is a new abstraction. Does this really match today’s reality? Are engineers going to solve multicore programming problems for advanced graphics or achieve 1Gbps wireless communication throughput only by working at a new level of abstraction? That would be surprising.
New thinking is required for system level design, just like we rethought RTL design in the 80s. Start with what the engineers are trying to do and work from this keystone. Provide something simple and effective that does the job.
In the past, horizontally oriented hardware description languages predominated. In the systems space, simplicity demands a vertically oriented, application-centric mindset, a blurring of the lines between tools and intellectual property, and a recognition that system design, once the purview of hardware engineers, will now shift to software designers as processors become the building blocks of the system.
Some companies are now taking a fresh look at systems design with interesting results. Let’s find a name to match!