Groundhog day

Groundhog dayIt’s Groundhog Day today. You’ve probably seen the movie Groundhog Day (netflix) in which the Bill Murray self-centered weatherman character is stuck in a time warp, waking up every morning to exactly the same day until, after re-examining his life, he doesn’t. Taping out a chip seems to be a bit like that, iterating trying to simultaneously meet budgets in a number of dimensions: area, timing and power. And, of course, schedule. Eventually, the cycle is broken and the chip tapes out.

There is a lot of iteration in chip design. The goal of EDA is to move as much of the iteration under the hood as possible. It is obviously not possible to manually try the type of iteration the synthesis or place and route tools do millions of times as they produce their results. To the user this seems like a linear process: read in the design, churn away, and write out the answer.

But when the user doesn’t get the result they wanted the Groundhog Day feeling begins. EDA tools are not all that easy to drive and most of the controls are somewhat indirect. Years ago I once drove an old car with a steering wheel mounted manual gear-shift. The linkage necessary to make the lever actually engage the shafts in the gearbox probably worked OK when the car had been new, but by the time I got to try, it was a secret art to move the lever just the right way to engage the gears. Controlling an EDA tool is like that only harder. There are many parameters with very poorly defined results that are not even really understood by the programmers who added them. Some of them are even documented!

The internal iterations of EDA tools are inevitably hard to control. The algorithms are all exponential and so rules-of-thumb need to be used to make them terminate at all. One complex algorithm really needs another inside its inner loops since a good placement is onethat routes well. But there obviously isn’t time to try millions of routes while finalizing a placement. And a good route is one that doesn’t cause timing problems, or crosstalk problems, or create features that can’t be manufactured and so on. It is amazing that anything works at all.

Each process node the problem seems to get harder since we add a new wrinkle. We used to have simple timing models that didn’t even worry about resistance or signal slew rate. We didn’t have to worry about crosstalk. We didn’t worry about power. There was no need for resolution enhancement technologies since we were using light with a shorter wavelength than the feature sizes.

The latest Groundhog Day wrinkle is process variability along with the sheer difficulty of closing so many budgets simultaneously. The black-belt groups whose job is to get chips out where other groups are struggling are finding that they have to do more manual intervention than they are used to: more floorplanning, manual placement, structured placement of datapaths and so on. This seems to be the way of the future. There is so much knowledge about the design that is needed for success than is captured through the design process. With that knowledge designers can find out whether it is still Groundhog Day or whether it is finally February 3rd and time to tape out.

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