I’ve given lots of keynote speeches about EDA over the years. You too can give your own keynote if you follow these simple secret guidelines.
Ladies and gentlemen…
Moore’s law…blah, blah, blah. Show generic Moore’s law slide. New challenges. Scary.
Design gap…blah, blah, blah. Show generic design gap slide. Must close the gap. Scary.
Chips are getting bigger, more physical effects are becoming important, wavelength used for lithography is not changing, engineering productivity must increase.
The three mega-trends: drive up the level of abstraction for greater productivity, drive down the level of detail since second-order effects are becoming first-order, and increase integration to improve productivity.
So far everything has been completely generic. You could have given the same speech a decade ago. If you did, it is a good idea to at least update the years on your generic slides so they don’t finish five years in the past. Now it’s time to get vaguely specific. You’ll need to update the rest of the keynote at least every process node. That’s only every couple of years so not too much work.
Talk about big issues of the day that affects everyone. Power is hot (or perhaps that should be cool) or how about process variability, or impact of new lithography restrictions. If you talk about power, talk about how power format standards (or at least the one you support) will make everything straightforward. Don’t forget how committed you are to standards.
Drive up level of abstraction so that front-end designers are more productive. Talk about the architectural level; nobody is quite sure what it is but it is big picture so wave your hands a lot. Maybe talk unconvincingly about need to take embedded software into account. The audience knows nothing about it but they have whole groups doing it, and they are bigger than the IC groups, so it must be important. Talk about importance of IP and doing design using much larger blocks. This is a good time to talk about standards again and how committed you are to them. System-C and transactional-level modeling are good names to drop. Verification is 60% of cost of design. Tradeoffs need to be done at architectural level for greatest effect, later in the design cycle is too, uh, late.
Drive down level of detail so that we take into account new physical and manufacturing effects we used to be able to ignore. “You can’t ignore the physics any more” makes it sound like you didn’t forget all the physics you learned in college. Designers need to worry about process variability and will need statistical timing tools to worry with. And after thirty years of pretty much putting what we want onto masks we are not going to be able to do that any more. Good moment to have scary pictures of the difference in how layout looks on the screen to the mask to the silicon.
Need for greater productivity. Next generation databases. If yours is open, argue about why this is public spirited, sustainable and green. If yours is closed, argue about how that enables your tools to be more optimized and efficient. Everyone needs more integrated tools. Nothing is fast enough so your tools will all be multi-threaded one day. Soon. You hope. Flows are important. Unless you only have point tools in which case talk about how best-in-class point tools are even better than flows.
You are short on time so slip in a quick mention of manufacturing test. Who knows anything about it? But chips have to be tested so talk about scan. Or BIST. Or ScanBIST. Then there’s packaging and printed circuit boards. They are probably important too, but everyone in the audience is a chip designer. Best not to think too much about them.
They don’t design FPGAs either, but good to mention them to show you understand how widely they are used. But there’s no money in EDA for FPGAs so best to gloss over exactly what capabilities you have.
Wrap it up and get off the stage. We are working hard on all these areas. We are your partner for the future.