In the 1980s, chip design was focused on layout: cramming all those gates into as few chips as possible, trying make use of every square millimeter of silicon. The 1990s were the decade of timing, when all the tools became timing driven with a completely synchronous design methodology. Of course area was still important but the biggest headache for designers was closing timing. The 2000s seem to be the decade of power, where the biggest headache is now meeting the power budget.
In the past, each process generation was accompanied by a reduction in power supply voltage so that it was possible to push up the frequency. Especially since voltage is squared in the power equation. However, that game has come to an end since reducing the voltage takes it too close to the threshold voltage and transistors will not turn off properly. That is why, in particular, microprocessors have gone multi-core rather than having 10GHz frequencies. Their power density would be the same as in the core of a nuclear reactor, not too suitable for a server never mind a laptop.
In tomorrow’s post I’ll summarize the techniques available for power reduction. Having recently been interim CEO of a startup company in the power reduction business, I know a lot more than I used to. But a fundamental problem is that almost any technique requires changes to a large number of tools. For example, if the chip has two power supply voltages, a gate may have two different performances depending on which block it is used in. The simulator needs to know that to get the timing right. But Vdd and Vss don’t occur explicitly in the netlist. This is mainly for historical reasons since they didn’t occur explicitly in schematics either. Besides, back then there was only one of each so there wasn’t the possibility for ambiguity.
The CPF and UPF standards were the most recent EDA standard war. It looks like another Verilog/VHDL standoff where both sides sort of win, and tools will need to be agnostic and support both. Both standards are really a way of documenting power intent for the techniques for power reduction that advanced design groups have struggled to do manually. CPF (common power format, but think of the C as Cadence, although it is officially under SI2 now) seems slightly more powerful than UPF (universal power format, but think of the universal as Synopsys, Magma and Mentor, although it is officially under Accelera now and is on track to becoming an IEEE standard P1801). CPF and UPF attempt to separate the power architecture from everything else so that changes can be made without requiring, in particular, changes to the RTL.
Both standards do a lot of additional detailed housekeeping, but one important thing that they do is to define for each group of gates which power supply they are attached to so that all tools can pick the correct performance, hook up the correct wires, select the right library elements during synthesis, know when a block is turned off and so on.
The detailed housekeeping that the standard formats take care of acknowledge that the netlist is not independent of the power architecture. If two blocks are attached to power supplies with different voltages, then any signals between the two blocks need to go through level shifters to ensure that signals switch properly. But they don’t appear explicitly in the netlist. Since those level shifters will eventually be inserted at place and route, any earlier tools that analyze the netlist need to consider them too or they will be confused.
If a block is powered down, then output signals need to be tied to either Vdd or Vss since otherwise they will drift to an intermediate value creating a partially active path from Vdd to Vss through both the P and N transistors of gates in the fanout. This will dissipate power: not good. But again, these cells, which don’t appear in the netlist, will eventually be inserted and so will affect timing. During powerdown, it is also possible that some register values need to be preserved, meaning that special retention registers that take a third always-on power supply must be used.
The purpose of the CPF and UPF formats is to make it explicit what these changes to the netlist are so that all tools in the flow make the same decision and are not surprised to find, say, an isolation cell in the layout that doesn’t correspond to anything in the input netlist. Or, indeed, an isolation cell missing in the layout, which should have been inserted despite the fact that it doesn’t appear in the input netlist either.
You can learn a lot about low-power techniques by reading the tutorial documents and presentations on the various websites associated with these two important standards.