For sale, a fab, cost $40/second

Posted on February 19, 2009 by paulmcl

Semiconductor technology is a mass-production technology. Enormous functionality can be delivered in a chip that costs a few dollars. But only if you want to buy a lot of them. Further, to keep Moore’s Law on track, the scale of manufacture keeps increasing. Chips were originally manufactured on circular wafers that were 2” in diameter, cramming as many of die onto the wafer as possible, and perhaps building a few wafers per day. Then wafers became 4”, 6”, 8”. Today the latest fabs use 12” wafers and may manufacture 50,000 wafers a weekor more. At the same time, as the wafers have got larger the size of the elements on the chip have got smaller and smaller, going from over 10 microns to 45-90 nm today.

All the fab equipment is extremely expensive and the cost of a fab has gone from a few tens of millions of dollars to around $5-6B today. Since a fab has a useful lifetime of about three years, it depreciates at around $40/second. Taking into account all the other costs (silicon, design, marketing) means that to own a modern fab means a company must do business at $200/second or $6B/year. Few companies are this big and so not many companies, even those that call themselves semiconductor companies, can afford to own their own fabs any more. Jerry Sanders’s comment that “real men have fabs” is no longer true at all. Only Intel seems big enough to go it alone on the manufacturing side, along with TSMC and Samsung for DRAM.

None of this is particularly positive for EDA, or the non-IP bulk of EDA. Fewer chips produced in higher and higher volumes is the EDA nightmare. The EDA dream is hundreds of companies designing chips, many of which don’t even go into production, not far off the situation in the late 1980s and early 1990s when ASIC democratized design and pushed it out into the system companies. Not coincidentally this was also the heyday of EDA from a growth and business point of view.

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Guest blog: Mike Smayling

Posted on February 18, 2009 by paulmcl

Mike SmaylingToday’s guest blog is from Mike Smayling, who is the senior VP product technology at Tela Innovations. He has a background in both the semiconductor industry at Texas Instruments, and semiconductor equipment at Applied Materials. In a couple of earlier entries I looked at the implications of lithography on design, and on how a whole spectrum of DFM companies were launched and (largely) died. But when we get down to 32nm and below the rules for what we can put on masks will start to change significantly or there is simply no way to print them during lithography. Mike explains the background and a little of the Tela approach.

Gridded Design Rules with Lines and Cuts: the Shape of Things to Come

After over 50 years of lateral and vertical scaling of integrated circuit dimensions, we are approaching a fork in the roadmap. We need to choose between design “business as usual” or a new design style which gives an important degree-of-freedom to the overall patterning optimization problem.

The root cause of the current problem is illustrated by the Rayleigh equation,

Half-Pitch = k1 · wavelength / numerical-aperture or R = k1 l/NA.

The coefficient k1 is a fitting factor; lower k1 means more difficult lithography. With l/NA limited to 143nm, lower k1 will be the focus for reducing feature sizes.

Conventional IC layout uses “2D” shapes with bends, jogs, and other features which don’t get through an optical scanner “low pass filter.” The random shapes used to create random logic functions do not allow optimizing the photolithography systems. Instead, they force a “lowest-common-denominator” approach which ends up not getting the best usage of increasingly costly equipment.

There have been countless DFM panel sessions at numerous conferences discussing the problem. Experts have pointed out the growing number of design rules needed to communicate capabilities from the wafer fab to the design team. There have been other layers of design rules added, such as “recommended rules” and “restricted rules,” which attempt to either relax dimensions to improve yield or to restrict pattern-dependent combinations of dimensions to avoid potential yield problems.

Numerous DFM startups appeared with tools to predict “hot spots” or locations which were prone to necking or bridging problems within the process window. Later tools were able to give repair recommendations or even fix problems. Unfortunately, most of the tools had claims like “we fix over 90% of your hotspots.”

An interesting approach to improving the overall patterning system has been SMO (source – mask optimization). This involves trying different illuminator shapes, like annular, dipole, or cross-pole, to address the source issue, and different OPC (optical proximity correction) approaches to address the mask issue. Very complex solutions can be found using computational lithography, in which both the source and the mask can be pixilated with different intensity/polarization and transmission at each pixel. Of course, there are issues with the illuminator stability and qualification, and issues with mask manufacture and inspection.

The other tine of the fork leads away from CDR (complex design rules) toward GDR (gridded design rules). GDR layouts using “1D” lines can be fabricated at lower k1 values than complex 2D layouts. The Tela Canvas is a GDR approach which has been shown to give competitive area at lower dimensional variability using standard patterning.

An important benefit of GDR will be realized when SMO is extended to include design rules in the optimization. This is possible because GDR involves a small set of rules like width, space, and end-gap for each line level, and width and space for hole levels. Large regions of design space can be mapped out to demonstrate where hotspots are, and rules can be set which avoid problem regions.

An additional benefit of GDR will come from improving the ability of wafer fabs to do failure analysis. A harsh reality for DFM companies is that wafer fabs are ultimately responsible for yield. This means that anything that can be done from the design side to simplify incoming patterns and variations in patterns will ultimately improve yield.

For advanced technology nodes, like 32nm and below, it is straightforward to extend GDR by using “lines and cuts.” In this approach, a layout is decomposed into two patterns: one for straight lines, the other for cuts which define where breaks are created in the final lines. Lines and cuts are already common in the gate level of 45nm CMOS logic, where it adds value in the SRAM bit cell by reducing the tip-to-tip gate spacing. Recent examples of 22nm half-pitch patterns done with lines and cuts show that there is no patterning barrier down to 16nm logic dimensions.

One dimensional layoutLines and cuts allow each patterning system to be separately optimized. SMO can be effective to get better use from lithography systems for lines, as is done with NAND Flash memories today. The cut patterns can also be optimized for optical lithography, or with relatively low pattern densities, could be handled by multiple-e-beam systems.

Anyone who has done classical filter design knows that cancelling poles and zeros is easy in principle but difficult in practice. The complex path will lead to a more costly solution as 2D patterning systems are used at ultra-low k1 values. The 1D Tela path stays with relatively simple solutions today, and delays the need for complex SMO for 2-3 generations.

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DFM: Design for manufacturing

Posted on February 17, 2009 by paulmcl

OPCYesterday I gave a brief overview of lithography and the need for DFM tools to calculate and verify what needs to go on the mask so that we end up with what we want on the die.

The need to continue using 193nm light at the 90nm technology node created a discontinuity. Ad hoc approaches would not longer be enough. Venture capitalists realized this was an opportunity, and also a number of manufacturing companies that had some relevant software internally They created about thirty EDA companies in the early 2000s. There were also some existing companies that moved to bring products to market in the space.

In a cohort of companies founded to address a problem, there is a winner-take-all dynamic. This is true of most industries, not just EDA. Most of the profit goes to the #1 player, some goes to the #2 player and #3 on down pretty much either break even or lose money. For startups, the #1 player is acquired for a lot of money, #2 for a reasonable sum, and everyone else become what VCs optimistically call a technology sale, meaning they’ll take whatever they can get to get it off their hands.

The earliest company into the space was OPC solutions, which was probably too early. Mentor acquired it in 1998 and used as a starting point for its DFM solutions in Calibre, which is still the market leader in OPC. Then Numerical Technologies, which Synopsys acquired in 2003.

If we look at the next generation, the companies fall into three main groups.

Firstly, mask analysis: examining the polygons on the mask and checking whether they were matched what was meant to be there. This was mainly the province of the equipment vendors (plus Brion): KLA, AMAT, Brion, ASML and Nikon.

Next were the simulation companies. They would analyze the mask, work out the effect of all the wave interference of light in the stepper optics, simulate the lithography and work out what would end up on the wafer. This could then be used to check that it was close enough to the original layout, or to adjust timing or to search for hot spots, areas of the wafer where manufacturing problems (such as bridging of one piece of metal to another) were too statistically likely. Brion, Clearshape, ASML and Mentor all had products here.

Finally, optimization, working out the impact of the RET decoration and making changes to it to improve manufacturing yield. ClearShape and Blaze played here.

But there were dozens of other companies. Process optimization with HPL Technology, IC Scope, ISE, PAL, PDF solutions, Sigma-C, Silvaco, Stone Pillar, Syntricity. Preventing catastrophic failures and increasing yields were Anchor, CMP, Bindkey, ESCad, Prediction software, ChipMD, Invarium, , Ubitech and Xyalis. Hot spot tools and critical area identification came from Ponte, Mentor, Cadence, Synopsys. Mask optimization produced another group consisting of Aprio, ASML masktools, Blaze, Brion, K2, Clearshape, Fortis, IC Scope, Magma/Mojave, Takumi and, of course, Mentor’s Calibre. Phew, that’s a lot of companies and I’m sure I’ve probably missed some too.

You will notice that most of these companies are no longer around. Actually they are around, just not independent.  The big successes among the startups were Brion, which was acquired by ASML (a lithographic equipment company) for about $270M and Clearshape (acquired by Cadence for around $50M). K2 was also acquired by Cadence for an undisclosed, supposedly not large, sum.

Mentor’s Calibre is probably still the market leader in OPC. Next are Synopsys’s DFM tools which originally came from TMA (via Avant!) and Numerical Technologies. Cadence, despite a few acquisitions, are an also-ran. PDF solutions still exists (it is a public company). Blaze (which had already absorbed Aprio) existed as late as last November and its assets will show up somewhere soon. Takumi still exists, mostly doing business in Japan. Anchor still exists, with Xillinx among others as a customer. The rest are mostly gone or, in some cases, reabsorbed back into the parent that they were optimistically spun out of.

So what is the moral of the story. As usual, one conclusion is the venture capitalists make sheep look like independent thinkers. Every VC that invested in EDA wanted to have a play in the DFM space.

Another observation is that the technology was tricky: optics is not a normal part of EDA. The business models were trickier: did you sell to design groups, the manufacturing groups in fabless companies, the foundries themselves or the mask houses? How statistical (manufacturing) versus pass/fail (design) did you make things? Did you get a royalty of some sort or just license fees?

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Lithography for dummies (well, us EDA guys)

Posted on February 16, 2009 by paulmcl

You probably already know that designs are transferred onto chips using a photographic process. The wafer is coated in a solution called photoresist and then exposed to light passed through a “mask” which alters its chemical composition. The exposed (or sometimes unexposed, depending on type ) photoresist is then removed with a powerful acid and some semiconductor process takes place through the gaps created: diffusion of impurities, implantation of ions, etching of metal and so forth.

Originally a mask was the size of an entire wafer and all the die (technically the plural of die is dice but it looks so Las Vegas I’ll stick with die) were exposed to light at the same time through a mask the same size as the wafer (which was 2”, 3” or 4” back then; now they are 12” with 18” in planning). For about the last twenty years, though, each die has been exposed individually through a reticle, a smaller mask that is stepped across the chip one die at a time by an expensive piece of equipment called a stepper. Usually the reticle is a multiple of the actual die size and the stepper has reduction optics rather like a photographic enlarger in reverse.

Originally we used 436nm mercury lamps which was a much shorter wavelength than the 1um or so feature size we were trying to achieve on the die so we didn’t have to worry about all those strange things in optics that you may remember from high-school or college physics: Young’s slits, diffraction gratings, wave interference. What was drawn on the layout designer’s screen, what was put on the mask and what ended up on the silicon were pretty much the same thing.

As feature sizes got smaller, we reduced the wavelength of light, first to 248nm and then to 193nm. We are still at 193nm for two reasons. We had developed technology for DUV (deep-ultra-violet) at 157nm but it was really expensive and unattractive. We also discovered immersion lithography where the gap between the lens and the wafer is filled with water not air, which improves things enough that we can continue to use 193nm for the time being.

The basic problem is that as the wavelength gets shorter and shorter, we are moving out of the part of the electromagnetic spectrum where we can focus light with lenses, and into the part where we essentially have X-rays that go straight through the lens and through pretty much anything else too. The next step looks like it will have to be e-beam lithography, where a beam of electrons is steered in the same way as in an old TV. This is well-understood technically but it has a very slow write speed which, so far, makes the whole process uneconomical for mass production.

But being stuck at 193nm means we have a new problem. We have feature sizes on chips that are much less than 193nm (which is around 0.18um which was many process nodes ago). All sorts of optical effects happen due to wave interference of light and we needed to put very different patterns on the mask from the original layout, in order to get the eventual feature on the die to match what we first thought of. It became anything but WYSIWYG.

There is a whole gamut of techniques that have come to be known as RET, for resolution enhancement technologies. Optical proximity correction (OPC) changes the shape of what is on the mask so that what ends up on the wafer is what is required. For example, corners have extra lumps added so that they don’t get etched away. Phase shift masking (PSM) etches the reticle by fractions of a wavelength so that the interference that results is desirable. The generic name for putting these extra features onto the mask is known as RET decoration. Since this might multiply the billion or so shapes on a layer by a factor of ten it is computationally very expensive.


A whole subsegment of EDA grew up when this first became important, under the generic name of DFM, design for manufacturability. Many companies were started in the segment and it is instructive to look at this since it is the most recent example of an area of technology where the basic cycle from foundation to exit is pretty much complete. That can wait until another day.

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Request

Posted on February 13, 2009 by paulmcl

Margarita, mmmmI’m actually on vacation in Mexico next week, in fact I should be on a plane as you read this, but we never go dark here and the blog will continue under autopilot. In fact it will be lithography week, with several entries on various aspects of how optics affect design.

A few comments on the blog in general, which has been going for about 6 weeks now. In general I don’t reply directly to comments in the comments. If enough interesting points are made then I can always revisit the subject, after all I have a whole blog. However, I do read them all and I think that the few entries that have attractive extensive comments have produced an interesting discussion.

If there are subjects that you would like to see covered then comment on this entry (or any other) with your ideas. You can always do that anonymously if you feel your suggestion is career limiting. Of course you can always send me email directly: paul at greenfolder dot com.

So you’ve got a week to get your requests in. Otherwise I shall continue to write about whatever happens to interest me.

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One hit wonders

Posted on February 13, 2009 by paulmcl

Spirit in the skyVenture capitalists have the concept of a zombie. Just like in the movies, a zombie company is one of the living dead. It is a company that is not burning through cash, and so is not going to go bankrupt if starved of further investment. On the other hand, it is not doing well enough that it has any exit possibilities. Venture capitalists have a fuse burning on their funds though, and generally 7 to 10 years after they first raised money for the fund they want to be able to close it down and do the final accounting: so many companies were sold for nice gain, so many ran out of money and so on.

But zombies make this difficult since they are not dead yet and could even go on for years growing slowly, successfully funding operations out of revenue but never achieving a growth rate that is going to interest another company in a merger or acquisition, never throwing off enough profit to make a merger with anyone accretive.

In this scenario, VCs will push companies to try something, anything, that might create success, even with the attendant risk of total failure. VCs like the answer to be clear even though the employees would rather simply have a job for a long time. Simply winding up the company is unattractive since, say, $1M for a technology sale is so close to zero as to be the same thing, so if there is any risky chance of quickly making the company genuinely successful that is more attractive.

Public companies can get into this state too, not doing well enough to go anywhere but not doing badly enough to die. Their stock price languishes since there is no chance that anyone is going to try and acquire the company as for its running business, and little chance that the company is going to break out and become a star performer.

For example, at one point soon after I left VLSI Technology their market cap (their share price times the number of shares outstanding) was not only less than their book value (the value of all their capital equipment, buildings, investments and cash) but less than the cash they had in the bank. In theory it should be possible to buy the company using its own cash (ignoring any premium).

This is not just like buying a house with no money down, it is like buying a house for $500K when you know there is $600K in the master-bedroom closet. It is a vote of no-confidence by the shareholders, an acknowledgement that the company is in the value destroying business. Of course VLSI at that cheap price was attractive and Philips Semicondutors (now NXP) bought it for its wireless business with Ericsson and people who knew how to get an process node into production a year or two faster than NXP was able to do with their conservative approach.

A company that is currently in this sort of shape is California Micro Devices (CAMD). Their stock price today is $2.18 with 23.55M shares outstanding. So their market cap is $51.35M. Their last four quarters of revenue totaled just over $60M on which they lost less than $1M. They can go on for a long time like that.

But they have $51.6M of cash and $66.9M of current assets (accounts receivable, inventory, short-term investments) and only $10.3M of debt. So their market cap is equal to their cash, and about half the value of simply winding up the company (probably not all the current assets would be realizable in this scenario though). It is like the house with the money in the closet.

Everyone knows that if they run the business as usual they will simply waste that cash. There is really no reason not to simply wind up the company and return the money to the shareholders, giving them about a 100% premium. But at the same time everyone knows they are not going to do that which is why the stock price does not reflect the break-up value.

Fabless semiconductor companies often have a single hit and make a lot of money on that first chip. Portal Player, who made the sound chip in the first iPods are a good example. But, if they are not acquired, they sometimes go on to burn that money trying to follow up their first hit with a second only to discover like Little Eva (Locomotion) or Norman Greenbaum (Spirit in the sky) that they are a one-hit-wonder.

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Survival of the fittest EDA companies

Posted on February 12, 2009 by paulmcl

Charles DarwinIt’s the 200th anniversary of Darwin’s birthday today. Not to mention Abraham Lincoln’s. On a personal note, Darwin went to university at Edinburgh and then Cambridge (the real one in England, not that one near Boston), as did I but in the opposite order (although I managed to graduate from both; he dropped out from Edinburgh after two years studying medicine there, which he apparently hated, but the biology building is named after him anyway).

One of the things that I find most odd about the US, along with pretty much any other immigrant and almost everyone in Silicon Valley period, is the politicization of evolution. It doesn’t seem to be that way in any other country. Evolution there is treated the same way as, say, thermodynamics. It is settled science despite the fact that there are minor disputes about little details around the edges. Politicians are not expected to have an opinion on evolution any more than they are expected to have an opinion on entropy (“during my administration entropy will no longer increase at the rate it has been doing over the last eight years”). Even mainstream Christianity, Catholicism for example, regards evolution as God’s way of guiding development rather than pretending it doesn’t exist.

A lot of people are under the assumption that Darwin and evolution has something to say about the origin of life. It does not, it only discuses how development proceeds once life has begun. The origin of life on earth remains an interesting mystery. There is a wonderful overview in chapter two of Casti’s book Paradigms Lost (which unfortunately seems to be out of print now; it is a wonderful read). I assume this is a bit out of date but the Wikipedia entry on abiogenesis doesn’t seem to cover much more than Casti.

I think the controversy about evolution, and that about nature/nurture or sexual differences, stems from the fact that what we would like to be true turns out not to be. We would like to think we are the pinnacle of some constructive biological process rather than the outcome of messy evolution, just like we would like to think that our impact as parents and educators has more impact on our children than is the case, or that men and women really are identical blank slates at birth. The trouble is that it just isn’t so. For example, here is Bryan Caplan summarizing current results on bringing up children: “within the normal range of parenting styles, how you raise your children has little effect on how your children turn out.”

So which EDA companies are going to turn out to be the fittest and survive? I think it is clear that most of the current batch of startups are going to get starved of further funding and are going to run out of money. One or two will be very successful and get picked up by either Cadence or Synopys. Some will become zombies, companies that are slightly cash-flow positive (or even slightly negative) so that they don’t need additional funding, but are not growing fast enough to interest anyone in acquiring them. They will join the batch of current zombies, EDA companies that have been around for years and are not-dead-yet athough I expect some of these will not weather the current downturn.

The Darwinian survivors look to me to be Cadence, Synopsys and Mentor. I think the prospects are poor for almost everyone else. So that leaves us with 2½ EDA companies.

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The book that changed everything

Posted on February 11, 2009 by paulmcl

Until 1979, IC design was done by specialists who understood every aspect of the design from semiconductor fabrication, transistor characteristics, all the way up to small blocks of a maybe a thousand gates which was the limit of chip fabrication in that era. In the late 1970s this “tall thin man” approach started to break down. Design was getting too complex for people who understood the process to do it, and the process was getting sufficiently complex to become the realm of its own specialists.

Everything changed thirty years ago with the publication of Mead and Conway’s book “Introduction to VLSI systems.” It is out of print but it was the most influential book in semiconductor design and design automation ever.

Mead and Conway separated design from manufacturing by creating simplified design rules for layout, and a simplified timing model suitable for digital design. No longer was it necessary to understand every nuance of the fabrication process, no longer was it necessary to consider every transistor as an analog device. The most important aspect of this is that it meant that computer scientists could design digital chips since they no longer needed deep electrical engineering knowledge.

I was at Edinburgh University at the time, finishing up my PhD (in computer science, not electrical engineering). John Gray, who had run Carver Mead’s silicon structures project at Caltech on sabbatical from Edinburgh returned carrying galley proofs of the yet-to-be-published Mead and Conway book. He ran a course based on this, one of the first on IC design in the UK I presume, heavily attended not just by the students who were meant to be on the course but by many of us faculty too.

Design became the province of computer scientists who understood enough about layout, enough about timing, enough about architecture and enough about test to successfully create state-of-the-art chips. Indeed, they could do so more effectively than the electrical engineers since chips were getting to be too large to do entirely by hand, and computer scientists already knew how to deal with complexity. They also started to create the first EDA tools, simple layout editors, simple simulators, rudimentary design rule checkers, because their natural instincts were never to do anything by hand if you could create a program to automate it.

Mead and Conway’s book created a cohort of IC-literate computer scientists who went on to populate the CAD groups of the semiconductor companies and, eventually, the EDA industry once it got going.

To see how big a difference it made, look at analog design versus digital design today. Analog design is largely done today the way digital design was done until Mead and Conway: deeply expert designers with the raw process models, raw design rules and polygons.

The next big change would be the invention of Verilog and RTL synthesis that meant that computer scientists could design complex chips with almost no knowledge of how chips worked, what a transistor was, how a chip was made. This new layer meant that front end designers and back end designers were different people with different skill-sets.

We seem to be on the cusp of another such layer with ESL tools starting to become much more widely used, allowing designers with very little hardware knowledge at all to create complex systems. The layer above that is software, already well-understood and with its own culture and tools.

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EDA: not boring enough

Posted on February 10, 2009 by paulmcl

EDA is fun. Innovation is fun and not many businesses require as much innovation as EDA. Working in an EDA startup in particular was (and still can be) a lot of fun because the ratio of innovation to meetings, company politics and the rest is much higher.

But one effect of this has been that too many people want to start EDA companies. It is not as bad as Web 2.0 companies, and with the current freeze in EDA investment it is over for the time-being and maybe forever.

One piece of advice I remember seeing, I forget where, is never to do a job that has significant non-monetary compensation for doing it. Too many people will want to do it for those other reasons. Everyone wants to open a restaurant, write a book, and be an actor.

The company where my son works in San Francisco advertised for a graphic designer on craigslist. They took the ad down again after over 200 people had applied for the job. They took the ad down after…four hours. Too many people want to be graphic designers because they think it is cool, or arty, rather than because it is a profitable business to which they are especially well suited.

The person sitting next to me on a flight to Chicago once told me that he was in the concrete business. He had a dozen concrete plants in towns you’ve never heard of in unfashionable parts of the mid-West. The economics were simple. A town can support one concrete plant but not two. Consequently the owner of a concrete plant has a sort of monopoly. Sure, a contractor can buy concrete from another plant, but that is one town over, perhaps an additional 50 miles round trip for the concrete truck, a cost that makes it non-competitive. His plants returned over 30% of their capital every year. Concrete is far more profitable than EDA and partly because it is so boring.

If that guy was our Dad and we inherited the business, I’m sure we could all run it. But we don’t even consider businesses like that because technology is more exciting. EDA is not badly paid by any means, but considering just how hard it is and how much training and knowledge is required it is not that well-paid either.

I’ve read (but not verified) that one very well paid group of consultants are people who do Cobol programming. Everyone wants to program next generation web applications using AJAX and Python, not some crusty programming language designed in the 1950s. How much further from the trendy cutting edge can you get.

Bill Deegan, a friend of mine, does the equivalent in the EDA world. Not the sexy EDA algorithms for him, he creates and maintains the build and Q/A systems without which the programmers don’t have a product. Usually his clients bring him in when the build system has been ignored by the hot-shot programmers for so long that they can barely build their product never mind release it to a customer. He describes it as like garbage collection (the kind with a truck, not recovering unused program memory). It’s not glamorous but it needs to be done, and done well, and just like garbage collection, things get really messy if it isn’t. You won’t be surprised to know that he is rarely idle.

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Magma must die

Posted on February 8, 2009 by paulmcl

Three kids plus oneActually, it doesn’t need to be Magma. I just agree with Isadore that it would be better for EDA if one of the full-line EDA suppliers went away. Magma is taking on the mantle of sick man of the industry now that Mike Fister and his team have moved on and Cadence no longer looks like it is going to implode imminently. Magma announced Friday that it would lay of another 17% of its workforce, on top of a bit more than 10% that went a few months ago.

Magma risks entering the death spiral, where lack of confidence in its ability to invest in next generation tools, or even its ability to survive at all, leads to defections which gradually make its demise a self-fulfilling prophecy. It is the EDA equivalent of a bank run. Magma could survive if they can invest enough in R&D, but it is hard to see how that can come simply from their revenue, and the external investment climate is challenging, to say the least.

Prices for EDA tools are simply too low to adequately fund the R&D that the semiconductor industry requires, as I discussed a few days ago as a sort of “tragedy of the commons.” That overall shortage of investment is aggravated by the need to keep 4 (or 3 depending on whether you count Mentor) RTL to GDSII flows current, which means that the 20% or so of EDA revenue that flows through to R&D is spread thinner because it is spread across that extra group.

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