Guest Blog: Isadore Katz

Posted on February 8, 2009 by paulmcl

Isadore KatzToday’s guest blog is from Isadore Katz, CEO of CLK Design Automation. He has been in EDA for 20 years at Chrysalis, Cadence, Metasoft (Hspice) and even escaping EDA for a time as CEO of Lightchip before the gravitational pull of CLK brought him back in.

Four Companies Enter, Three Companies Leave

The current thinking these days is that anyone attempting an EDA start-up is an idiot. The VC’s are uninterested, exits are few and far between, and the chance of an IPO is zero. As the CEO of an EDA start-up company, I guess that makes me Idiot in Chief. So take everything I am about to say with a grain of salt; say the size of Grand Cooley Blog.

There are too many IC tool EDA companies. Not start-ups, there are always too many start-ups, but big IC EDA suppliers. Two is company, three’s a crowd, and four – four is just bad news. One of them has to go.

Both the semiconductor industry and EDA have to restructure in order to survive. The semiconductor houses must establish some level of pricing power with their customers. The world does not need 10 IC shops selling weakly differentiated wireless components to four handset manufacturers. Likewise the EDA industry needs to regain leverage. We do not need four major vendors supplying strained, front-to-back flows that get discounted to the point of oblivion.

Today all four EDA majors are trying to compete for the same business from the same 30 semiconductor shops, all of which are under severe margin pressure themselves. The result is an unmitigated disaster for all concerned.

Do the math. If four companies compete for 30 companies’ business, that averages out to 7.5 wins each. If 3 companies compete, its 10 wins each. More potential wins per major player means less discounting/higher revenue per customer, more top line revenue/bottom line profits and growth per major EDA vendor, and better industry performance. All of which should improve our image with investors, which ultimately should translate into improved market capitalization for all.

Why should the semiconductor companies care? Because the accountants’ persistent belief that EDA is a tax, and lots of inadequate, but heavily discounted, tools is a deal, is simply wrong. The real cost culprit is the difficulty of getting working silicon out of the tools. It is supposed to be electronic design automation, not 100 iteration, 50,000 lines of scripts per tool, sort-of-kind-of automation.

EDA’s job is to make the world’s most complicated version of Photoshop — including the camera/capture tools (but not the printer). There are at least 50 unique components to this flow. None of the big four does them all well. None of them can expect to maintain the level of innovation required to keep each of these at the leading edge needed for the latest process node. In fact, most of them have massive trailing edge commitments to customers that exist only as small font bullets in an archived PowerPoint presentation. Worse yet, some of them have a stunning trail of press releases promoting imaginary products. The current state of 4 major vendors with diminished pricing leverage and market caps will only perpetuate this condition.

With 3 healthier major EDA players, with market caps that reflect their revalue, focusing on what they do well, acquiring what they need, and making sure that producing 40nm and 32nm becomes practical and not just possible, maybe we have an industry.

Of course, I could be wrong. Even this may not be enough. In which case look for my future rant, “Three Companies enter, Two Companies leave.”

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He who goes first loses

Posted on February 6, 2009 by paulmcl

Chess moveEarlier we had guest blog entries from Lauro Rizzatti of EVE and Chi-Ping Hsu of Cadence on whether innovation occurs in small or large companies. I’ve always maintained that the problem is a different one. I think it is clear that the engineering groups of large companies are capable of creating leading edge technology. Look at any franchise product like Design Compiler, Virtuoso or Verilog simulation and see how it has advanced over many generations spread over a decade or more in ways that involve large amounts of innovation.

Where large companies have a problem is that they are very poor at introducing new products into their channels. They have large efficient sales organizations but those organizations are geared up to closing deals with customers for products that the customer already knows it wants. Unfortunately, when a brand new product is introduced, there is an attitude among the salespeople that “he who goes first loses.” But just as the Luddites really were right that automatic looms would put them out of business, the first person in a large company to sell a new product really does lose. There will be problems with the product that will tie up their application engineering resources for months, and potentially a large multi-million dollar deal will be held hostage to problems in a single copy of a hundred-thousand dollar tool. Better simply not to sell the product until enough other sales have been made for it to be mature. But with every salesperson taking this attitude, no sales occur.

This can extend even to products that are acquired. When Cadence purchased Ambit’s synthesis product line, it was obviously very strategic for Cadence salespeople to sell it aggressively. If they were successful, it would start to cut off money flowing to Synopsys and even if they were less successful, they would force Synopsys to circle the wagons to protect its Design Compiler franchise and so have less effort available to put into threatening Cadence’s huge place and route franchise. But Cadence salespeople would not. They had big quotas at big semiconductor companies to close, and their focus was to let Synopsys have synthesis and try and close a deal to supply everything else. Selling synthesis against Synopsys required extra effort and the payback of a few experimental licenses would not move the needle on their quota.

Another product from my time at Cadence was called Heck (at least internally, I forget what unmemorable name it got given externally). It was a formal verification tool built on some technology developed at Cadence Berkeley Labs. To tell the truth, I’ve no idea whether it was any good or not, but since the salespeople refused to try and sell it we never found out. In the end Cadence acquired Verplex and the Conformal product line that customers were already starting to adopt.

Very few products have been successfully introduced by large EDA companies (once they have become large). By successful I mean built up into $100M per year businesses. And by product I mean a genuinely new product line, not a new version of an existing product. The only one I can think of is Calibre. This was developed over the years inside Mentor and somehow survived being canceled for almost a decade before coming to dominate physical verification. Cadence helped by making a huge misstep. They tried to protect their Dracula franchise by making their hierarchical DRC Vampire require incompatible rule decks. Mentor had no such qualms and as a result the obvious upgrade path from Dracula was to Calibre not Vampire.

Synopsys made PrimeTime a big success, but the story is complicated by the fact that they acquired Viewlogic and with it Motive, the market leader in static timing. They then shut down Motive and transferred all its customers to PrimeTime. But undeniably they did manage to get their salesforce to sell it.

So I think that it is not so much that large EDA companies are incapable of innovation. They do it all the time. But their salesforces are reluctant to sell any product for which there is not already strong market pull. Marketing in EDA is unable to create that demand either, which is a different story.

However, startups are different. The salesforce will sell new products because the salesforce typically has precisely one product to sell, and it is new. They are not really the same sort of salesperson either. Startup salespeople are more like hunters whereas large company salespeople are farmers. It seems to take that combination of single mindedness in the salesforce and an entire company whose success depends on getting those initial customers to adopt the product. Once customers start to clamor for the product, it is the moment for a large EDA company to acquire the startup and the huge machine of their salesforce can drive the bookings number up very rapidly.

 

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Semiconductor is not EDA

Posted on February 5, 2009 by paulmcl

Executives from semiconductor companies regularly arrive in EDA companies convinced that their years of experience as customers mean that they understand the EDA business. Software people just need some of the discipline of semiconductor design, which the executive has plenty of, and a miraculous transformation will take place.

This view of the world makes the assumption that creating EDA software is just like creating a chip. After all, designing a chip is done in Verilog, which is just a language, so how different can it be?

On the business side, it makes the assumption that selling software is just like selling silicon. After all, it is a technical sale, you take an order, you ship a product, how different can it be?

A lot.

On the engineering side, a chip has a definitive event when it tapes out. Software is never done. There are probably parts of Design Compiler shipping today that is code written in the late 1980s. Intel’s latest microprocessor or TI’s latest GSM chip or whatever doesn’t contain stuff that old. Yes, IP blocks get reused, but not for decades. Even IP blocks have a different dynamic. If you need to cut a corner to get an IP block to work in your design, then you do it and tape out. If you find a bug in some software component then it needs to get fixed back at the canonical source. Otherwise, since the software lasts forever, there will forever be two versions, one containing your quick and dirty fix and one without. The result is that in software everything is much more inter-related than a semiconductor designer expects a lot of is it older than expected, and as a result there is also lots of code that works but is not well understood. Software development is just messier, and over time it gets worse. The de facto development methodology always deteriorates into big ball of mud.

There is also a different tradeoff in shipping a bug. Intel’s cost to fix the floating point bug or nVidia’s cost to fix their heating issues are hundred million dollar or billion dollar problems. While everyone has probably seen those tables showing that the cost of fixing a software bug once shipped is hundreds of times the cost of fixing it while the software is still in development, it is simply not a million dollar problem. Only products like the space shuttle guidance code can afford to spend astronomical(!) amounts on testing and have a long enough schedule to accommodate it. EDA software can’t support that on either economical or schedule grounds. As a result, IC design really is more disciplined and spends a large amount, upwards of 60% of effort, on verification and almost no software can do that. When software is released it is not a bet the company event since bugs can be fixed.

The scale of software is also bigger. There may be billions of transistors on a chip, but many of them are in regular structures of one sort or another. No software is in regular structures or else it would have been further abstracted to get rid of the repetition. The number one rule in software development is to keep each thing in only one place. Cisco’s IOS operating systems for routers is 25,000,000 lines of code. It is probably not clean but, by and large, there will not be a lot of duplication within it. It really is 25M lines of unique code. Chips do not consist of 25 million lines of Verilog.

On the business side there is an interesting difference between software and semiconductor. Firstly, semiconductor products typically have a lead time of the order of a quarter in length. This means that at the start of a quarter almost all the orders that will be produced that quarter are already in. Additional inventory might be built if there is spare capacity, in the hopes of selling it during the quarter (known as ‘turns business’). Software really can receive an order at 11pm on the last day of the quarter and ship it for revenue before midnight.

However, the more interesting different dynamic is in negotiating. When a purchasing agent negotiates with an EDA salesperson they both know the marginal cost of the software: zero. It really doesn’t cost any more to ship an additional copy of a software product. Semiconductor companies make sure that their salespeople do not know the manufacturing cost of the product (whether their cost models are good enough that they actually know it themselves is a different question). Marketing gives the salesman a price and perhaps some flexibility but neither the buyer nor the salesperson knows where the limits really are. Negotiations can be drawn out and nasty but there is a time aspect. If the buyer draws out the negotiations too long, they will not get their order submitted in time to get the product built. A software buyer knows that the biggest discount is likely as the quarter closes, and that the software company will still make incremental revenue no matter how big the discount.

There are probably other significant differences, but successful semiconductor experts can easily burn their fingers in the EDA business.

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Ferrari vs Formula-1

Posted on February 4, 2009 by paulmcl

It used to be received wisdom that the way to get a good design flow was for a semiconductor company to purchase best-in-class point tools and then integrate them together themselves. I think there were two reasons for this. First, the EDA companies had grown from a lot of acquisitions so that’s what they had for sale: good point tools that were poorly integrated. Second, they were selling to CAD groups in an era when semiconductor was doing well and CAD groups liked to justify their existence by doing lots of evaluation (which point tool is best?) and then integrating them (need lots of people).

For most people, this was actually not the best way to get a productive environment matched to their needs. It is as if we all had to buy cars the way a Formula-1 team does, buying the best engine, the best brakes, the best gearbox and making everything work well together ourselves at great expense. If you really need to win a Formula-1 race then this is the only way to go. Even a top of the line Ferrari is simply way too slow. But for most of us, a Honda Accord is just fine, easier to use, cheaper to acquire, and orders of magnitude less expensive to get and keep on the road.

Back in that era I was at VLSI Technology. When we spun out Compass we had a Honda Accord in a marketplace where people thought they wanted to build their own Formula-1 racecar. Potential customers only wanted to benchmark point tools and wouldn’t even attempt to benchmark an entire design flow. I’m not even sure how you would. I don’t know how much better the design flows that CAD groups assembled out of Cadence and Synopsys point tools (along with a seasoning of stuff from startups) really were. And neither does anyone else. They were certainly incredibly expensive in comparison. Before the spinout, I made several visits to semiconductor companies whose CAD groups were bigger than VLSI’s Design Technology group. But Design Technology developed all the tools, wrote all the source code for synthesis, simulation, timing analysis, place and route, physical verification, designed all the standard cell libraries, created the memory compilers and the datapath compiler. Soup to nuts. I think the only external tool in wide use was for gate-array place and route, an area where VLSI was never that competitive anyway (if you really wanted a gate-array, you went to LSI Logic).

Magma was the first and only EDA company to build an integrated environment. A CAD manager friend of mine told me that they used Magma for everything they could. For the most difficult designs they used Cadence’s Silicon Ensemble but they could train someone on Magma in a day (and they weren’t immediately hired away by the competition once they’d been expensively put through training).

At the EDAC forecast meeting a couple of weeks ago, Aart de Geus said he has been preaching that an integrated flow is important for years. One difference he is noticing in the current downturn, he said, is that this time executives are listening. Chi-Ping Hsu of Cadence told me the same thing about the Cadence PFI initiative which was well-received by power-sensitive customers (is there another sort of customer?). PFI’s main thread, the CPF standard, pulled together tools from across Cadence’s product line along with standards that allowed external tools to play in the flow too. Synopsys UPF does the same thing on their side of the standard wars trench. People had managed to put together power-aware flows before, lashing together point tools with lots of their own scripts. But they were very buggy and many chips failed due to trivial things like missing isolators or not taking getting the timing right in multi-voltage blocks. This seems to be a thing of the past now, although most designs are still on the basic end of power saving (fixed voltage islands, power-down) and not yet attempting the really tricky things like dynamic voltage and frequency scaling (lowering the voltage and slowing the clock when there is not much to do).

In the current hyper-cost-sensitive environment I think that the pendulum will swing back the other way towards these more pre-integrated flows and away from the integrate-your-own-point-tools approach. It is also the only way that complex factors like power, that cut across the whole design flow, can be accommodated. The slowing of startup acquisitions by the majors feeds into this, giving them time to put the effort into integration without constantly gaining more things to integrate. The integration has enormous value despite the fact that customers have been historically reluctant to pay vendors for it. When I was at Cadence we had some research showing customers spent $3 or so on integration for every $1 that Cadence got. So customers were paying for it, just not externally.

Not exactly on-topic, but you can actually see a Formula-1 car race a Ferrari and a Fiat.

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The arrogance of ESL

Posted on February 3, 2009 by paulmcl

Cell phonesESL, or electronic system level design, is a catchall term for tools above the level of RTL. There are two primary aspects to this: synthesis and verification of IC designs from representations higher than RTL (usually untimed C or System-C); and tools that do something to address development of the software component of electronic systems.

I have no problem with the term ESL for the first of these segments, synthesis and verification. There are several EDA companies (Mentor with Catapult, Forte, Synfora, CriticalBlue, AutoESL, Cadence C-to-silicon) providing synthesis and one (Calypto) providing formal verification of this level of design. Getting design productivity up higher than pumping out RTL Verilog is necessary and these companies, despite their limited success, are probably part of the solution.

But when EDA companies turn to the software space they look at everything through their IC spectacles and assume that ESL methodologies in the chip design world will have some part to play in development of the software that runs on the chips. They have IC bias. But the software component of electronic systems is much larger and much longer-lived than the hardware (chip) part. ESL thinking that it will impact software development is the tail trying to wag the dog.

I was at a keynote by the CTO of Cisco a couple of years ago. He revealed that IOS, Cisco’s router software and operating system, is 25 million lines of code and there are an additional 35 million lines of scripts for testing it. Consequently the number one priority for any chip being sold to go into a Cisco router is “don’t break the software.” This is way ahead of anything to do with chip area, performance, power dissipation and so forth. Indeed, I heard (anecdotally, so this is hearsay) that Cavium, who have a 16 core MIPS processor, were unable to penetrate Cisco since IOS isn’t multi-threaded enough to take advantage of all those cores. The chip has no problems and is probably desirable in all sorts of other dimensions but it breaks the software so game-over.

I once asked some embedded software developers at an electronic system company what they thought about ESL. This was fairly soon after I had joined VaST and still suffered myself from IC bias. I was expecting them to say it was promising, or they hated SystemC or something like that. Instead, they could only think of ‘English as a second language’ and had never even heard of ESL. Almost no software runs directly on the bare chip in any case, it is all intermediated by a real-time operating system such as Wind River’s VxWorks, Green Hills’s Integrity or, increasingly, some flavor of Linux (which includes OS-X on iPhone and Android on the Google-phone). This makes direct software-hardware co-design, where some of the code is optionally implemented in hardware, much more complex. Pulling out a block of software for synthesis into custom hardware (or for implementation on a special data-plane processor) requires the stubbed out software to make operating system calls to access a custom device driver that can talk to the custom hardware directly. Automating that process requires building not just the hardware, but the device driver and other operating system scaffolding, as well as the stub back in the original source code. Of course, that is completely operating system dependent and so requires multiple implementations.

Software people simply don’t care how the chip was designed. The models created as part of the hardware design process are too slow by factors of thousands or even millions to be useful as part of the software development process. But most importantly, the bulk of the software payload for the chip already exists in the form of previous versions of the product. Even a brand new product like iPhone carried over a lot of software from the Mac that was simply cross compiled to run on the iPhone’s ARM processor.

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Groundhog day

Posted on February 2, 2009 by paulmcl

Groundhog dayIt’s Groundhog Day today. You’ve probably seen the movie Groundhog Day (netflix) in which the Bill Murray self-centered weatherman character is stuck in a time warp, waking up every morning to exactly the same day until, after re-examining his life, he doesn’t. Taping out a chip seems to be a bit like that, iterating trying to simultaneously meet budgets in a number of dimensions: area, timing and power. And, of course, schedule. Eventually, the cycle is broken and the chip tapes out.

There is a lot of iteration in chip design. The goal of EDA is to move as much of the iteration under the hood as possible. It is obviously not possible to manually try the type of iteration the synthesis or place and route tools do millions of times as they produce their results. To the user this seems like a linear process: read in the design, churn away, and write out the answer.

But when the user doesn’t get the result they wanted the Groundhog Day feeling begins. EDA tools are not all that easy to drive and most of the controls are somewhat indirect. Years ago I once drove an old car with a steering wheel mounted manual gear-shift. The linkage necessary to make the lever actually engage the shafts in the gearbox probably worked OK when the car had been new, but by the time I got to try, it was a secret art to move the lever just the right way to engage the gears. Controlling an EDA tool is like that only harder. There are many parameters with very poorly defined results that are not even really understood by the programmers who added them. Some of them are even documented!

The internal iterations of EDA tools are inevitably hard to control. The algorithms are all exponential and so rules-of-thumb need to be used to make them terminate at all. One complex algorithm really needs another inside its inner loops since a good placement is onethat routes well. But there obviously isn’t time to try millions of routes while finalizing a placement. And a good route is one that doesn’t cause timing problems, or crosstalk problems, or create features that can’t be manufactured and so on. It is amazing that anything works at all.

Each process node the problem seems to get harder since we add a new wrinkle. We used to have simple timing models that didn’t even worry about resistance or signal slew rate. We didn’t have to worry about crosstalk. We didn’t worry about power. There was no need for resolution enhancement technologies since we were using light with a shorter wavelength than the feature sizes.

The latest Groundhog Day wrinkle is process variability along with the sheer difficulty of closing so many budgets simultaneously. The black-belt groups whose job is to get chips out where other groups are struggling are finding that they have to do more manual intervention than they are used to: more floorplanning, manual placement, structured placement of datapaths and so on. This seems to be the way of the future. There is so much knowledge about the design that is needed for success than is captured through the design process. With that knowledge designers can find out whether it is still Groundhog Day or whether it is finally February 3rd and time to tape out.

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“The tragedy of the commons” and EDA

Posted on January 30, 2009 by paulmcl

Fishing boatThe tragedy of the commons is an article published in Science magazine in 1968 by Garrett Hardin. It has since become very well known and is applicable widely when resources are shared without a market. The canonical example is common land being over-grazed or a common ocean being over-fished. It is in every fisherman’s interest to fish as much as he can even though he knows that the area is being over-fished. If fishes a bit more than his quota (assuming there is one) he gets to keep all the value of the extra fish but the cost of the over-fishing is spread among all the other fisherman.

So what does this have to do with EDA?

Each semiconductor company knows that they need EDA investment in R&D to be healthy. However, when they negotiate with the EDA vendors, of course they want to get the lowest price possible. They get all the money they save, but the impact of the reduced revenue is spread among them and all their competitors, perhaps a 5% problem for them.

But just like over-fishing the oceans, each vendor pursuing this strategy means that EDA risks being starved for investment. Each semiconductor company’s dream is that they get their EDA software for almost nothing, but that all the other semiconductor companies over-pay so EDA has plenty to invest. But that is not the situation we are in today, even before the recent economic chaos.

In one of the comments to an earlier entry somebody was pointing out that EDA is dead, using the Monty Python dead parrot sketch (“This parrot is no more! He has ceased to be!”) to emphasize the point. If EDA was, say, the newspaper industry then this would be unarguable. The only debate is when, and how, and what comes next. But EDA is not a buggy-whip business, it cannot go away. It can only change its form. As a venture investment, I agree it is dead. As a business, probably not. And as a technology, certainly not.

Since almost all electronics depends on semiconductors and since semiconductors can only be designed with EDA tools, this is a potential problem brewing. Electronics is about 3 trillion dollars, semiconductor is about 400 billion dollars, and EDA is just 5 billion. It is tempting to think of EDA as a hair attempting to wag the tail and have the tail wag the dog. But EDA is more like the pituitary gland, a tiny bit of the animal but without which nothing else works.

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Venture capital for your grandmother

Posted on January 29, 2009 by paulmcl

Like many of us in Silicon Valley, I often encounter people (hi Dad!) who don’t understand venture capital. I don’t mean all the details, I mean just the basic way investment is done in a startup. Often, even employees in startups don’t understand it either. Here’s how I explain it.

Let’s say you’ve got a good idea for a company, and you have done some work on it to produce a prototype. Maybe at this stage there are two of you. You have the prototype, the team (the two of you) and a business plan. Let’s say everyone agrees it is worth $1M at this point. We’ll ignore how that valuation was arrived at, although it is somewhat like buying a house, you (seller) want a higher valuation and the VC (buyer) wants lower so the valuation depends on the going rate for that sort of company and somewhat on how desperate you are to sell and how enthusiastic the VC is to buy. So you and your partner each have stock in your brand new company worth $500K. But you can’t just sell the company at this stage, companies like that don’t have any buyers at all. You need to make it more successful first.

So you decide you need some investment money, so you can pay yourselves and hire some more employees. You convince a venture capitalist that your company is going places and he or she wants to put in $500K. Everyone agreed that the company is worth $1M before this happens. This is called the pre-money valuation. The VC wires $500K to your bank account and you give them stock for 1/3 of the company. Suddenly your company is worth $1.5M, consisting of $1M for the company as it was the day before, plus another $500K sitting in the company bank account. This is called the post-money valuation. So you and your partner each own 1/3 of the company and the VC owns 1/3 of the company. But the valuation is higher so your 1/3 is worth $500K, exactly the same as your 1/2 was worth the day before. You’ve neither lost nor gained anything.

So what have you given up? A share of the future gains. You used to own 100% of the company with your partner, now you only own 2/3 of the company. If the company suddenly becomes worth $60M then you each have $20M and the VC has $20M (the VC has a preferred stock, which is different from what you and your partner probably have, so this might not be precisely accurate but it is close enough). What you gave up was that if the company was suddenly worth $60M before, you and your partner would have $30M each. But realistically, that wasn’t going to happen because you didn’t have enough money on your own to fund the company over time. So if this scenario plays out you get a nice payout. But, of course, if the company becomes worthless then everyone’s share goes to zero. 1/3 of zero is zero.

You might assume that if the company nearly goes bankrupt and is sold for just, say, $300K that you’d have 1/3 of it, namely $100K. But that is where the biggest difference between preferred stock and your stock comes to light. The preferred stock is so called because it gets preferential treatment and in this scenario the VC gets all of the money. You have a loss of $500K but then you never put in any real money so it is a paper loss. The VC has a very real loss of $200K since they put in $500K, you spent it, and the company pretty much failed.

Tomorrow, full-ratchet anti-dilution provisions and piggy-back rights. Well, maybe not.

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Guest blog: Chi-Ping Hsu

Posted on January 28, 2009 by paulmcl

Chi-PingOur second guest blog comes from Chi-Ping Hsu, who is senior VP of R&D for the implementation group at Cadence. Chi-Ping echoes Joy’s law that it is the people that are important and that innovation may be found anywhere, not least in large companies who have deeper resources to back up large-scale ideas. 

Innovation: it’s a personal thing

It’s always with some humor when I hear the claim that innovation comes only from startups. Most of these “startups” with many years of trials of ideas are not startups anymore. As a rule of thumb, after four years, the company is no longer a startup - it is a small company whose idea did not yet get off the ground the way they had planned. With fewer resources than larger companies, these small companies can easily disappear into an uncertain global economy or vanish in their own business bumps.

I have worked in all types of companies – true startups, small companies and large companies.  The truth is that innovation comes from people, and it really does not matter if those people are working in a new startup, an older small company, or a large established company.  It comes from people with vision.  However, the vision is merely the starting point.  It takes people with a true passion and drive for that vision to make it materialize.

Innovation also cannot occur in a vacuum.  It is a synthesis of accumulated experience, refined into an overall stratagem and approach.  Again, this synthesis comes from people and is not a property of an organizational scale.

Small companies must focus their limited resources on a problem of limited scope in order to get to market within the timeframe of their cash burn constraints and the patience limits of their investors.  The “point” solutions that result from startup/small company efforts are possible because of the relatively minimal investment required (just a few good people, armed with machines and some office space).  So, a small amount of capital can launch the hopes and dreams of many, and the hundreds of small companies in the EDA space are a perfect testament to that truth.  However, only a very small percentage of these companies reach any measure of success.  I have been lucky to have been through the process with a number of these successes, such as Quickturn, Avanti, and Get2Chip.

In my experience inside large organizations, it is still the passion of drive of the individual that sparks and brings to life innovation.  Because of the larger resource pool, big companies can contemplate multiple “point” ideas, along with large scale ideas that far transcend the value of any point ideas that small companies must practically stick with to survive.  Calibre comes to mind as a point innovation given birth by a large organization.

In my own more recent experience, the Power Forward Initiative is an example of a large scale innovation, spanning thirteen product technologies at Cadence, but then also reaching into the broader ecosystem of foundries, IP companies, service organizations, and the chip design community at large. Virtuoso is another example of a broad scale solution innovation that was born from passion within a large organization.  That is an area where we are seeing “re-innovation,” and it is really exciting to see.

The bottom line on innovation is that it is the people.  Large company or small company, innovators with management skill and market vision can make breakthroughs animate.  It’s the people.  It’s a personal thing!

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Guest blog: Lauro Rizzatti

Posted on January 28, 2009 by paulmcl

Lauro RizzatiToday’s we have two guest blogs. First Lauro Rizzatti, who is general manager of EVE-USA, an emulation company. Despite his Italian name, Lauro is the US manager of a French-based emulation company. He takes a look at whether small or large companies are the source of innovation in EDA. As an executive for a small company, he takes the small-is-beautiful side of the argument.

Innovation comes in small packages

While the debate rages on, it’s clear that in the emulation space that tools from smaller and more nimble companies’ such as EVE are winning the contest as next-generation emulation becomes an increasing important verification tool.

Emulation has been around since the dawn of commercial EDA 25 years ago and has been used to supplement software simulation. Since then, chip designers have used a wide variety of off-the-shelf FPGA-based emulators or custom emulators from large and small vendors (Zycad, IKOS, Quickturn, Mentor/Meta…) with varying degrees of success. EVE is turning this market segment upside down by unveiling an emulator based on standard FPGAs that’s set to end-of-life the traditional custom-based emulator. 

Formal verification is another example. After a monumental failure by a large EDA vendor in the late 1990s, the industry wrote it off as a classic example of theoretical study that could not be applied to the commercial world. Since 2000 or so, companies such as Real Intent and its model checking software have proven the naysayers wrong. Verplex Systems and its equivalence checker were so successful that Cadence acquired it in 2003.

And, who could forget the success of tiny Co-Design Automation Inc. that produced the next-generation Verilog language SystemVerilog? Its founder Simon Davidmann and his team placed SystemVerilog, known then as SUPERLOG, into the public domain and it became an instant de facto standard. Synopsys snapped up Co-Design in 2002.

Perhaps it’s a result of focus and a small R&D team that gives a startup or small company the freedom to take a fresh approach such as these. Or in the case of emulation, the $200 million market cap is not big enough for a large EDA vendor to justify $30 million to develop a custom chip. A small company has the ability to offer a more cost-effective means for design and re-tooling.

Performance and price are important considerations, especially when selecting an emulation platform, and a startup or smaller company is often able to win these evaluation categories. 

Startups and smaller companies can be more aggressive in identifying and responding to trends. A recent example is the way in which software is making the difference as the design team mix changes and co-verification strategies need to be considered. The smaller EDA vendors were quicker to react as the ratio of software engineers to hardware designers grew to ten to one, making emulators a handy tool for testing the integration of hardware and software.

Today more than ever, innovation comes from EDA startups and smaller companies. This is apparent in the emulation space as standard FPGA-based emulation solutions from smaller companies assume the leadership role, though other EDA segments are dominated by startups as well.It’s the age-old debate within the EDA industry: Are smaller companies more innovative and able to produce more breakthrough technologies compared to their larger, established competitors?

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