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Last week was the EDAC Kauffman Award dinner. One minor advantage of being a blogger is that I got invited along as press. “Will blog for food”. This year’s winner was Professor Randal Bryant, usually just known as Randy Bryant.

I knew of Randy as the inventor of switch level simulation with a tool called MOSSIM. Up until that point, all simulation of semiconductor had been done using Spice type algorithms, worrying about the transfer functions of the transistors. But with the coming of Mead and Conway, computer scientists were starting to want a much simpler model of the world so that they could apply programming techniques to design. Treat transistors as switches that were either on or off and with a unit delay (all transistors turned on and off at the same speed). MOSSIM was the first of these so-called switch level simulators developed in about 1980. At VLSI we developed a similar tool, called VSIM. Later, the switch model would be enhanced to add timing (and, surprise, ours was called TSIM). Funny now to realize that in the early 1980s IC design was largely done without timing, using Spice for paths that looked like they might be important.

Randy Bryant was also the inventor of BDDs, binary decision diagrams. BDDs are a very efficient representation of combinational logic and are one of the key technologies underlying logic optimization and hence underlying both synthesis and formal verification. The advantage of BDDs is that despite being a fairly compressed  representation of the circuit, many logic operations can be done efficiently directly on the BDD, without needing to expand the representation into something less space efficient and then recompress it again afterwards. They are not good at representing everything; multipliers are notorious for exploding BDD size but they are hard to represent period.

Randy first published his ideas in 1986. An amazing fact that came to light at the Kauffman award dinner was that his paper just kept getting more and more citations. Usually a paper generates a flurry of interest soon after publication and then it dies down. But 15 years after publication for most of the early part of this decade, Randy’s paper wasn’t just the most cited paper in EDA, it was the most cited paper in the whole of computer science.

The Kauffman Award is awarded based on the impact that individuals have had on EDA. The ideas in MOSSIM, while very important in the early 1980s have dwindled in importance since as simulation has moved up to higher levels. But given that every synthesis and formal verification tool relies heavily on BDDs over 20 years after their conception I think that the “impact” is unarguable.

Yesterday at ICCAD, Jim Hogan and I led an discussion on the megatrends facing electronics and the implications going forward for EDA. Basically we took a leaf out of Scoop Nisker’s book, who when he finished reading the news would sign off with "if you don’t like the news go out and make some of your own." So we tried to.

Anyone whose being reading this blog regularly won’t be surprised at the position that we took. I managed to find some interesting data from Morgan Stanley about how electronics is growing but it is also fragmenting. PCs ship in 100s of millions; cell-phones in billions (the world is expected to get to 100% penetration in a couple of years) and the fragmented consumer market in 10s of billions: car electronics, mobile video, home entertainment, games, kindles, iPods, smart-phones and so on.

So the end market is growing strongly but individual systems (with a few exceptions) are shipping in smaller individual volumes.

Meanwhile, over in IC-land the cost of design has been rising rapidly. For a 45nm chip it is now $50M. There are two problems with this for EDA. One is that the sticker price means that a lot fewer chips will be designed, and second that the fastest growing part of the cost is software (where EDA doesn’t play much) now up to almost 2/3 the cost of design. But if a chip costs $50M to design then you’d better be shipping it into a market of 250M+ units or the economics won’t work.

So we have a mismatch: fragmented consumer market requiring low-cost low-volume designs. Semiconductor economics requiring high-cost high-volume designs.

The only way around this is aggregation at the silicon level, along with reconfigurability and reprogrammability.

The most basic form of aggregation is the FPGA, since the basic gates can be used for pretty much any digital design. It’s not very efficient in terms of area or power, but it is completely flexible.

The second form of aggregation is the programmable SoC. This is something I’ve predicted for some time but I was surprised to discover recently that some manufacturers have been building these for several years. Indeed, Cypress gave me a chart showing that they are on track to ship 3/4 billion of this by the end of the year and should pass a billion next year. The programmable SoC doesn’t have completely uncommitted gates like an FPGA, rather it has little building blocks for peripherals, both analog and digital, that can be reconfigured into a wide range of different devices. This can either be done one time to initialize the device, or it can be done dynamically under control of the on-board processor(s).

The third form of aggregation is the platform. This seems to be most successful in the wireless world, TI’s OMAP being the most well-known. But it has also been happening in digital video. At some point it become more efficient to waste silicon by loading up a chip with everything you might ever want, and enable/disable by software, as opposed to eating the huge cost of masks and inventory of specializing each derivative to perfectly match the end customers needs.

Jim carried on to talk about which type of products make money in EDA. There is a range of types of tools from measurement, modeling, analysis, simulation and optimization. The further to the right on this list the more money customers are prepared to pay and the most likely it will be that you can create and sustain a competitive advantage for several years. Each tool needs to be better, faster or cheaper and preferably all three in order to be successful. If you can only have two they’d better be better and faster. Cheaper in EDA has the same connotations as low-cost heart surgeon. With so much on the line that’s not the place to economize.

Ultimately this is moving towards what I call software signoff, the inversion of the way about thinking about electronic systems. Instead of thinking of a complex SoC with some embedded software, a system is actually a big software system, parts of which need to be accelerated by some type of semiconductor implementation to make them economic (fast enough, low enough power). We don’t have the tools today to take complex software and automatically build some parts in gates, assemble IP, assign the software to processors and so on. But that is the direction we need to move in.

The mismatch between fragmented end-markets and high costs of design is potentially disruptive and thus an opportunity to change the way that design is done. I return to Yoshihito Kondo of Sony’s call to arms: "We don’t want our engineers writing Verilog, we want them inventing concepts and transferring them into silicon and software using automated processes."

The presentation is posted on the SI2 website here.

It was only a couple of weeks ago that I was writing about software-signoff and FPGAs. I mentioned that Synopsys didn’t really have any high-level synthesis. Rumor has it that they do have sequential formal verification in development. Anyway, on Monday they announced Synphony which they position as high-level synthesis. Synopsys has musical product names now, not just Cadence.

Unlike other high-level synthesis it doesn’t start from C or C++ or SystemC. It starts from M, which is the language used within Matlab, the system development environment of The Mathworks. A lot of system design, especially in radio and automotive, is done using Mathworks products. They are a private company with a huge number of seats that sell at that intermediate price point which seems cheap for an EDA tool but expensive for a PC tool. More than Photoshop but less than Verilog. They also distribute their software widely within universities. As a result, M and Mathlab (along with various associated products like Simulink) are the primary tool today for algorithm exploration.

I think that this is worth looking at for a couple of reasons. First, it is another step towards the new world where more and more design is done at levels disconnected from chip design by people who don’t think of themselves as chip designers. And then automated tools reduce this to RTL and then to an FPGA (or gates).

The second thing worth looking at is The Mathworks themselves. They are selling at a low price point, rumored to be very profitable, sell an enormous number of licenses and are firmly on the cutting edge of technology. IC design automation can’t do this, of course. There just aren’t enough designers. But once you start to think of FPGA as being the implementation of choice, after all “almost all” designs will be FPGAs going forward, it’s not clear that is true. The low end “fred in a shed” FPGA design is never going to invest in tools. But the big new FPGA designs need powerful tools just as much and, in aggregate, will be a big market.

Somewhat on a similar note, at ICCAD Jim Hogan and I will be talking about  “How EDA needs to change” which, surprise, will tie into this theme. It will be in the Silicon Valley Room at the DoubleTree at 3pm on Monday November 2nd. See you there.